939 lines
35 KiB
C++
939 lines
35 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#include "param_names.h"
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#include "iodev/iodev.h"
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#if BX_SUPPORT_X86_64==0
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// Make life easier merging cpu64 & cpu code.
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#define RIP EIP
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#define RSP ESP
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#endif
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::long_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error, Bit16u error_code)
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{
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bx_descriptor_t gate_descriptor, cs_descriptor;
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bx_selector_t cs_selector;
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// interrupt vector must be within IDT table limits,
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// else #GP(vector*8 + 2 + EXT)
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if ((vector*16 + 15) > BX_CPU_THIS_PTR idtr.limit) {
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BX_ERROR(("interrupt(long mode): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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Bit64u desctmp1 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16);
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Bit64u desctmp2 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16 + 8);
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if (desctmp2 & BX_CONST64(0x00001F0000000000)) {
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BX_ERROR(("interrupt(long mode): IDT entry extended attributes DWORD4 TYPE != 0"));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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Bit32u dword1 = GET32L(desctmp1);
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Bit32u dword2 = GET32H(desctmp1);
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Bit32u dword3 = GET32L(desctmp2);
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ((gate_descriptor.valid==0) || gate_descriptor.segment)
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{
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BX_ERROR(("interrupt(long mode): gate descriptor is not valid sys seg"));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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// descriptor AR byte must indicate interrupt gate, trap gate,
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// or task gate, else #GP(vector*8 + 2 + EXT)
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if (gate_descriptor.type != BX_386_INTERRUPT_GATE &&
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gate_descriptor.type != BX_386_TRAP_GATE)
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{
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BX_ERROR(("interrupt(long mode): unsupported gate type %u",
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(unsigned) gate_descriptor.type));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (soft_int && gate_descriptor.dpl < CPL)
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{
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BX_ERROR(("interrupt(long mode): soft_int && gate.dpl < CPL"));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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if (! IS_PRESENT(gate_descriptor)) {
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BX_ERROR(("interrupt(long mode): gate.p == 0"));
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exception(BX_NP_EXCEPTION, vector*8 + 2);
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}
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Bit16u gate_dest_selector = gate_descriptor.u.gate.dest_selector;
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Bit64u gate_dest_offset = ((Bit64u)dword3 << 32) |
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gate_descriptor.u.gate.dest_offset;
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unsigned ist = gate_descriptor.u.gate.param_count & 0x7;
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// examine CS selector and descriptor given in gate descriptor
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// selector must be non-null else #GP(EXT)
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if ((gate_dest_selector & 0xfffc) == 0) {
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BX_ERROR(("int_trap_gate(long mode): selector null"));
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exception(BX_GP_EXCEPTION, 0);
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}
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parse_selector(gate_dest_selector, &cs_selector);
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// selector must be within its descriptor table limits
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// else #GP(selector+EXT)
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &cs_descriptor);
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// descriptor AR byte must indicate code seg
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// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
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if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
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IS_DATA_SEGMENT(cs_descriptor.type) ||
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cs_descriptor.dpl > CPL)
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{
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BX_ERROR(("interrupt(long mode): not accessible or not code segment"));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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// check that it's a 64 bit segment
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if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b)
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{
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BX_ERROR(("interrupt(long mode): must be 64 bit segment"));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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// segment must be present, else #NP(selector + EXT)
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if (! IS_PRESENT(cs_descriptor)) {
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BX_ERROR(("interrupt(long mode): segment not present"));
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exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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Bit64u RSP_for_cpl_x;
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Bit64u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
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Bit64u old_RIP = RIP;
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Bit64u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
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Bit64u old_RSP = RSP;
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// if code segment is non-conforming and DPL < CPL then
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// INTERRUPT TO INNER PRIVILEGE:
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if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL)
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{
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BX_DEBUG(("interrupt(long mode): INTERRUPT TO INNER PRIVILEGE"));
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// check selector and descriptor for new stack in current TSS
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if (ist > 0) {
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BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
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RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
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}
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else {
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RSP_for_cpl_x = get_RSP_from_TSS(cs_descriptor.dpl);
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}
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// align stack
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RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
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// push old stack long pointer onto new stack
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write_new_stack_qword_64(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
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write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
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write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
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// push long pointer to return address onto new stack
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write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
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write_new_stack_qword_64(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
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RSP_for_cpl_x -= 40;
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if (push_error) {
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RSP_for_cpl_x -= 8;
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write_new_stack_qword_64(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
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}
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// load CS:RIP (guaranteed to be in 64 bit mode)
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branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, cs_descriptor.dpl);
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// set up null SS descriptor
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load_null_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], cs_descriptor.dpl);
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}
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else if(IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL)
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{
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// if code segment is conforming OR code segment DPL = CPL then
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// INTERRUPT TO SAME PRIVILEGE LEVEL:
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BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE"));
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// check selector and descriptor for new stack in current TSS
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if (ist > 0) {
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BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
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RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
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}
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else {
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RSP_for_cpl_x = RSP;
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}
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// align stack
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RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
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// push flags onto stack
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// push current CS selector onto stack
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// push return offset onto stack
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write_new_stack_qword_64(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
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write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
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write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
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// push long pointer to return address onto new stack
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write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
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write_new_stack_qword_64(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
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RSP_for_cpl_x -= 40;
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if (push_error) {
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RSP_for_cpl_x -= 8;
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write_new_stack_qword_64(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
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}
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// set the RPL field of CS to CPL
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branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, CPL);
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}
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else {
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BX_ERROR(("interrupt(long mode): bad descriptor type %u (CS.DPL=%u CPL=%u)",
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(unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl, (unsigned) CPL));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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RSP = RSP_for_cpl_x;
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// if interrupt gate then set IF to 0
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if (!(gate_descriptor.type & 1)) // even is int-gate
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BX_CPU_THIS_PTR clear_IF();
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BX_CPU_THIS_PTR clear_TF();
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//BX_CPU_THIS_PTR clear_VM(); // VM is clear in long mode
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BX_CPU_THIS_PTR clear_RF();
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BX_CPU_THIS_PTR clear_NT();
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}
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#endif
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void BX_CPU_C::protected_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error, Bit16u error_code)
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{
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bx_descriptor_t gate_descriptor, cs_descriptor;
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bx_selector_t cs_selector;
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Bit16u raw_tss_selector;
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bx_selector_t tss_selector;
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bx_descriptor_t tss_descriptor;
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Bit16u gate_dest_selector;
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Bit32u gate_dest_offset;
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// interrupt vector must be within IDT table limits,
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// else #GP(vector*8 + 2 + EXT)
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if ((vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) {
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BX_ERROR(("interrupt(): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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Bit64u desctmp = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*8);
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Bit32u dword1 = GET32L(desctmp);
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Bit32u dword2 = GET32H(desctmp);
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
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BX_ERROR(("interrupt(): gate descriptor is not valid sys seg (vector=0x%02x)", vector));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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// descriptor AR byte must indicate interrupt gate, trap gate,
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// or task gate, else #GP(vector*8 + 2 + EXT)
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switch (gate_descriptor.type) {
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case BX_TASK_GATE:
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case BX_286_INTERRUPT_GATE:
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case BX_286_TRAP_GATE:
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case BX_386_INTERRUPT_GATE:
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case BX_386_TRAP_GATE:
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break;
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default:
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BX_ERROR(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
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(unsigned) gate_descriptor.type));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (soft_int && gate_descriptor.dpl < CPL) {
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BX_ERROR(("interrupt(): soft_int && (gate.dpl < CPL)"));
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exception(BX_GP_EXCEPTION, vector*8 + 2);
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}
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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if (! IS_PRESENT(gate_descriptor)) {
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BX_ERROR(("interrupt(): gate not present"));
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exception(BX_NP_EXCEPTION, vector*8 + 2);
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}
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switch (gate_descriptor.type) {
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case BX_TASK_GATE:
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// examine selector to TSS, given in task gate descriptor
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raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
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parse_selector(raw_tss_selector, &tss_selector);
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// must specify global in the local/global bit,
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// else #GP(TSS selector)
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if (tss_selector.ti) {
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BX_ERROR(("interrupt(): tss_selector.ti=1 from gate descriptor - #GP(tss_selector)"));
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exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
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}
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// index must be within GDT limits, else #TS(TSS selector)
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fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &tss_descriptor);
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// AR byte must specify available TSS,
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// else #GP(TSS selector)
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if (tss_descriptor.valid==0 || tss_descriptor.segment) {
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BX_ERROR(("interrupt(): TSS selector points to invalid or bad TSS - #GP(tss_selector)"));
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exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
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}
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if (tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_286_TSS &&
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tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_386_TSS)
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{
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BX_ERROR(("interrupt(): TSS selector points to bad TSS - #GP(tss_selector)"));
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exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
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}
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// TSS must be present, else #NP(TSS selector)
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if (! IS_PRESENT(tss_descriptor)) {
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BX_ERROR(("interrupt(): TSS descriptor.p == 0"));
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exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc);
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}
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// switch tasks with nesting to TSS
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task_switch(0, &tss_selector, &tss_descriptor,
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BX_TASK_FROM_INT, dword1, dword2, push_error, error_code);
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return;
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case BX_286_INTERRUPT_GATE:
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case BX_286_TRAP_GATE:
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case BX_386_INTERRUPT_GATE:
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case BX_386_TRAP_GATE:
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gate_dest_selector = gate_descriptor.u.gate.dest_selector;
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gate_dest_offset = gate_descriptor.u.gate.dest_offset;
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// examine CS selector and descriptor given in gate descriptor
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// selector must be non-null else #GP(EXT)
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if ((gate_dest_selector & 0xfffc) == 0) {
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BX_ERROR(("int_trap_gate(): selector null"));
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exception(BX_GP_EXCEPTION, 0);
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}
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parse_selector(gate_dest_selector, &cs_selector);
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// selector must be within its descriptor table limits
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// else #GP(selector+EXT)
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &cs_descriptor);
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// descriptor AR byte must indicate code seg
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// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
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if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
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IS_DATA_SEGMENT(cs_descriptor.type) ||
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cs_descriptor.dpl > CPL)
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{
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BX_ERROR(("interrupt(): not accessible or not code segment cs=0x%04x", cs_selector.value));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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// segment must be present, else #NP(selector + EXT)
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if (! IS_PRESENT(cs_descriptor)) {
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BX_ERROR(("interrupt(): segment not present"));
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exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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// if code segment is non-conforming and DPL < CPL then
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// INTERRUPT TO INNER PRIVILEGE
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if(IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL)
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{
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Bit16u old_SS, old_CS, SS_for_cpl_x;
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Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
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bx_descriptor_t ss_descriptor;
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bx_selector_t ss_selector;
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int is_v8086_mode = v8086_mode();
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BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
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// check selector and descriptor for new stack in current TSS
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get_SS_ESP_from_TSS(cs_descriptor.dpl,
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&SS_for_cpl_x, &ESP_for_cpl_x);
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if (is_v8086_mode && cs_descriptor.dpl != 0) {
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// if code segment DPL != 0 then #GP(new code segment selector)
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BX_ERROR(("interrupt(): code segment DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
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}
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// Selector must be non-null else #TS(EXT)
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if ((SS_for_cpl_x & 0xfffc) == 0) {
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BX_ERROR(("interrupt(): SS selector null"));
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exception(BX_TS_EXCEPTION, 0); /* TS(ext) */
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}
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// selector index must be within its descriptor table limits
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// else #TS(SS selector + EXT)
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parse_selector(SS_for_cpl_x, &ss_selector);
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// fetch 2 dwords of descriptor; call handles out of limits checks
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
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parse_descriptor(dword1, dword2, &ss_descriptor);
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// selector rpl must = dpl of code segment,
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// else #TS(SS selector + ext)
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if (ss_selector.rpl != cs_descriptor.dpl) {
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BX_ERROR(("interrupt(): SS.rpl != CS.dpl"));
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exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
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}
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// stack seg DPL must = DPL of code segment,
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// else #TS(SS selector + ext)
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if (ss_descriptor.dpl != cs_descriptor.dpl) {
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BX_ERROR(("interrupt(): SS.dpl != CS.dpl"));
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exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
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}
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|
|
// descriptor must indicate writable data segment,
|
|
// else #TS(SS selector + EXT)
|
|
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
|
|
IS_CODE_SEGMENT(ss_descriptor.type) ||
|
|
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
|
|
{
|
|
BX_ERROR(("interrupt(): SS is not writable data segment"));
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
|
|
}
|
|
|
|
// seg must be present, else #SS(SS selector + ext)
|
|
if (! IS_PRESENT(ss_descriptor)) {
|
|
BX_ERROR(("interrupt(): SS not present"));
|
|
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc);
|
|
}
|
|
|
|
// IP must be within CS segment boundaries, else #GP(0)
|
|
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
|
BX_ERROR(("interrupt(): gate EIP > CS.limit"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
old_ESP = ESP;
|
|
old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
|
|
old_EIP = EIP;
|
|
old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
|
|
|
// Prepare new stack segment
|
|
bx_segment_reg_t new_stack;
|
|
new_stack.selector = ss_selector;
|
|
new_stack.cache = ss_descriptor;
|
|
new_stack.selector.rpl = cs_descriptor.dpl;
|
|
// add cpl to the selector value
|
|
new_stack.selector.value = (0xfffc & new_stack.selector.value) |
|
|
new_stack.selector.rpl;
|
|
|
|
if (ss_descriptor.u.segment.d_b) {
|
|
Bit32u temp_ESP = ESP_for_cpl_x;
|
|
|
|
if (is_v8086_mode)
|
|
{
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
temp_ESP -= 16;
|
|
}
|
|
else {
|
|
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
temp_ESP -= 8;
|
|
}
|
|
}
|
|
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
// push long pointer to old stack onto new stack
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, old_SS);
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_ESP);
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl, read_eflags());
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl, old_CS);
|
|
write_new_stack_dword_32(&new_stack, temp_ESP-20, cs_descriptor.dpl, old_EIP);
|
|
temp_ESP -= 20;
|
|
|
|
if (push_error) {
|
|
temp_ESP -= 4;
|
|
write_new_stack_dword_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
|
|
}
|
|
}
|
|
else { // 286 int/trap gate
|
|
// push long pointer to old stack onto new stack
|
|
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, old_SS);
|
|
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) old_ESP);
|
|
write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl, (Bit16u) read_eflags());
|
|
write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_CS);
|
|
write_new_stack_word_32(&new_stack, temp_ESP-10, cs_descriptor.dpl, (Bit16u) old_EIP);
|
|
temp_ESP -= 10;
|
|
|
|
if (push_error) {
|
|
temp_ESP -= 2;
|
|
write_new_stack_word_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
|
|
}
|
|
}
|
|
|
|
ESP = temp_ESP;
|
|
}
|
|
else {
|
|
Bit16u temp_SP = (Bit16u) ESP_for_cpl_x;
|
|
|
|
if (is_v8086_mode)
|
|
{
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
temp_SP -= 16;
|
|
}
|
|
else {
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
temp_SP -= 8;
|
|
}
|
|
}
|
|
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
// push long pointer to old stack onto new stack
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, old_SS);
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_ESP);
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl, read_eflags());
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl, old_CS);
|
|
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-20), cs_descriptor.dpl, old_EIP);
|
|
temp_SP -= 20;
|
|
|
|
if (push_error) {
|
|
temp_SP -= 4;
|
|
write_new_stack_dword_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
|
|
}
|
|
}
|
|
else { // 286 int/trap gate
|
|
// push long pointer to old stack onto new stack
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, old_SS);
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) old_ESP);
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl, (Bit16u) read_eflags());
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_CS);
|
|
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-10), cs_descriptor.dpl, (Bit16u) old_EIP);
|
|
temp_SP -= 10;
|
|
|
|
if (push_error) {
|
|
temp_SP -= 2;
|
|
write_new_stack_word_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
|
|
}
|
|
}
|
|
|
|
SP = temp_SP;
|
|
}
|
|
|
|
// load new CS:eIP values from gate
|
|
// set CPL to new code segment DPL
|
|
// set RPL of CS to CPL
|
|
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
|
|
|
|
// load new SS:eSP values from TSS
|
|
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
|
|
|
|
if (is_v8086_mode)
|
|
{
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
BX_DEBUG(("interrupt(): INTERRUPT TO SAME PRIVILEGE"));
|
|
|
|
if (v8086_mode() && (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl != 0)) {
|
|
// if code segment DPL != 0 then #GP(new code segment selector)
|
|
BX_ERROR(("interrupt(): code segment conforming or DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
|
|
}
|
|
|
|
// EIP must be in CS limit else #GP(0)
|
|
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
|
BX_ERROR(("interrupt(): IP > CS descriptor limit"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
// push flags onto stack
|
|
// push current CS selector onto stack
|
|
// push return offset onto stack
|
|
if (gate_descriptor.type >= 14) { // 386 gate
|
|
push_32(read_eflags());
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
push_32(EIP);
|
|
if (push_error)
|
|
push_32(error_code);
|
|
}
|
|
else { // 286 gate
|
|
push_16((Bit16u) read_eflags());
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
push_16(IP);
|
|
if (push_error)
|
|
push_16(error_code);
|
|
}
|
|
|
|
// load CS:IP from gate
|
|
// load CS descriptor
|
|
// set the RPL field of CS to CPL
|
|
load_cs(&cs_selector, &cs_descriptor, CPL);
|
|
}
|
|
|
|
EIP = gate_dest_offset;
|
|
|
|
// if interrupt gate then set IF to 0
|
|
if (!(gate_descriptor.type & 1)) // even is int-gate
|
|
BX_CPU_THIS_PTR clear_IF();
|
|
BX_CPU_THIS_PTR clear_TF();
|
|
BX_CPU_THIS_PTR clear_NT();
|
|
BX_CPU_THIS_PTR clear_VM();
|
|
BX_CPU_THIS_PTR clear_RF();
|
|
return;
|
|
|
|
default:
|
|
BX_PANIC(("bad descriptor type in interrupt()!"));
|
|
break;
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::real_mode_int(Bit8u vector, bx_bool push_error, Bit16u error_code)
|
|
{
|
|
if ((vector*4+3) > BX_CPU_THIS_PTR idtr.limit) {
|
|
BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
push_16((Bit16u) read_eflags());
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
push_16(IP);
|
|
|
|
Bit16u new_ip = system_read_word(BX_CPU_THIS_PTR idtr.base + 4 * vector);
|
|
// CS.LIMIT can't change when in real/v8086 mode
|
|
if (new_ip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
|
|
BX_ERROR(("interrupt(real mode): instruction pointer not within code segment limits"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
Bit16u cs_selector = system_read_word(BX_CPU_THIS_PTR idtr.base + 4 * vector + 2);
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
|
|
EIP = new_ip;
|
|
|
|
/* INT affects the following flags: I,T */
|
|
BX_CPU_THIS_PTR clear_IF();
|
|
BX_CPU_THIS_PTR clear_TF();
|
|
#if BX_CPU_LEVEL >= 4
|
|
BX_CPU_THIS_PTR clear_AC();
|
|
#endif
|
|
BX_CPU_THIS_PTR clear_RF();
|
|
}
|
|
|
|
void BX_CPU_C::interrupt(Bit8u vector, unsigned type, bx_bool push_error, Bit16u error_code)
|
|
{
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR show_flag |= Flag_intsig;
|
|
#if BX_DEBUG_LINUX
|
|
if (bx_dbg.linux_syscall) {
|
|
if (vector == 0x80) bx_dbg_linux_syscall(BX_CPU_ID);
|
|
}
|
|
#endif
|
|
bx_dbg_interrupt(BX_CPU_ID, vector, error_code);
|
|
#endif
|
|
|
|
BX_INSTR_INTERRUPT(BX_CPU_ID, vector);
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
bx_bool soft_int = 0;
|
|
switch(type) {
|
|
case BX_SOFTWARE_INTERRUPT:
|
|
case BX_SOFTWARE_EXCEPTION:
|
|
soft_int = 1;
|
|
break;
|
|
case BX_PRIVILEGED_SOFTWARE_INTERRUPT:
|
|
case BX_EXTERNAL_INTERRUPT:
|
|
case BX_NMI:
|
|
case BX_HARDWARE_EXCEPTION:
|
|
break;
|
|
|
|
default:
|
|
BX_PANIC(("interrupt(): unknown exception type %d", type));
|
|
}
|
|
|
|
BX_DEBUG(("interrupt(): vector = %02x, TYPE = %u, EXT = %u",
|
|
vector, type, (unsigned) BX_CPU_THIS_PTR EXT));
|
|
|
|
// Discard any traps and inhibits for new context; traps will
|
|
// resume upon return.
|
|
BX_CPU_THIS_PTR debug_trap = 0;
|
|
BX_CPU_THIS_PTR inhibit_mask = 0;
|
|
|
|
#if BX_SUPPORT_VMX || BX_SUPPORT_SVM
|
|
BX_CPU_THIS_PTR in_event = 1;
|
|
#endif
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (long_mode()) {
|
|
long_mode_int(vector, soft_int, push_error, error_code);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
RSP_SPECULATIVE;
|
|
|
|
// software interrupt can be redirefcted in v8086 mode
|
|
if (type != BX_SOFTWARE_INTERRUPT || !v8086_mode() || !v86_redirect_interrupt(vector))
|
|
{
|
|
if(real_mode()) {
|
|
real_mode_int(vector, push_error, error_code);
|
|
}
|
|
else {
|
|
protected_mode_int(vector, soft_int, push_error, error_code);
|
|
}
|
|
}
|
|
|
|
RSP_COMMIT;
|
|
}
|
|
|
|
#if BX_X86_DEBUGGER
|
|
BX_CPU_THIS_PTR in_repeat = 0;
|
|
#endif
|
|
|
|
#if BX_SUPPORT_VMX || BX_SUPPORT_SVM
|
|
BX_CPU_THIS_PTR in_event = 0;
|
|
#endif
|
|
}
|
|
|
|
/* Exception classes. These are used as indexes into the 'is_exception_OK'
|
|
* array below, and are stored in the 'exception' array also
|
|
*/
|
|
#define BX_ET_BENIGN 0
|
|
#define BX_ET_CONTRIBUTORY 1
|
|
#define BX_ET_PAGE_FAULT 2
|
|
|
|
#define BX_ET_DOUBLE_FAULT 10
|
|
|
|
static const bx_bool is_exception_OK[3][3] = {
|
|
{ 1, 1, 1 }, /* 1st exception is BENIGN */
|
|
{ 1, 0, 1 }, /* 1st exception is CONTRIBUTORY */
|
|
{ 1, 0, 0 } /* 1st exception is PAGE_FAULT */
|
|
};
|
|
|
|
#define BX_EXCEPTION_CLASS_TRAP 0
|
|
#define BX_EXCEPTION_CLASS_FAULT 1
|
|
#define BX_EXCEPTION_CLASS_ABORT 2
|
|
|
|
struct BxExceptionInfo exceptions_info[BX_CPU_HANDLED_EXCEPTIONS] = {
|
|
/* DE */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* DB */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 02 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // NMI
|
|
/* BP */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_TRAP, 0 },
|
|
/* OF */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_TRAP, 0 },
|
|
/* BR */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* UD */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* NM */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* DF */ { BX_ET_DOUBLE_FAULT, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
// coprocessor segment overrun (286,386 only)
|
|
/* 09 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* TS */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
/* NP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
/* SS */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
/* GP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
/* PF */ { BX_ET_PAGE_FAULT, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
/* 15 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // reserved
|
|
/* MF */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* AC */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 1 },
|
|
/* MC */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_ABORT, 0 },
|
|
/* XM */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 20 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 21 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 22 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 23 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 24 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 25 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 26 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 27 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 28 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
|
|
/* 29 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* 30 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // FIXME: SVM #SF
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/* 31 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }
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};
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|
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// vector: 0..255: vector in IDT
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// error_code: if exception generates and error, push this error code
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// trap: override exception class to TRAP
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|
void BX_CPU_C::exception(unsigned vector, Bit16u error_code)
|
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{
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BX_INSTR_EXCEPTION(BX_CPU_ID, vector, error_code);
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|
|
|
#if BX_DEBUGGER
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bx_dbg_exception(BX_CPU_ID, vector, error_code);
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#endif
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|
|
|
BX_DEBUG(("exception(0x%02x): error_code=%04x", vector, error_code));
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|
|
|
unsigned exception_type = 0;
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|
unsigned exception_class = BX_EXCEPTION_CLASS_FAULT;
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|
bx_bool push_error = 0;
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|
|
|
if (vector < BX_CPU_HANDLED_EXCEPTIONS) {
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|
push_error = exceptions_info[vector].push_error;
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|
exception_class = exceptions_info[vector].exception_class;
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|
exception_type = exceptions_info[vector].exception_type;
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|
}
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|
else {
|
|
BX_PANIC(("exception(%u): bad vector", vector));
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|
}
|
|
|
|
if (vector != BX_PF_EXCEPTION && vector != BX_DF_EXCEPTION) {
|
|
// Page faults have different format
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX
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|
VMexit_Event(0, BX_HARDWARE_EXCEPTION, vector, error_code, push_error);
|
|
#endif
|
|
|
|
#if BX_SUPPORT_SVM
|
|
SvmInterceptException(BX_HARDWARE_EXCEPTION, vector, error_code, push_error);
|
|
#endif
|
|
|
|
if (BX_CPU_THIS_PTR errorno > 0) {
|
|
if (BX_CPU_THIS_PTR errorno > 2 || BX_CPU_THIS_PTR curr_exception == BX_ET_DOUBLE_FAULT) {
|
|
// restore RIP/RSP to value before error occurred
|
|
RIP = BX_CPU_THIS_PTR prev_rip;
|
|
if (BX_CPU_THIS_PTR speculative_rsp)
|
|
RSP = BX_CPU_THIS_PTR prev_rsp;
|
|
|
|
debug(BX_CPU_THIS_PTR prev_rip); // print debug information to the log
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_TripleFault();
|
|
#endif
|
|
#if BX_DEBUGGER
|
|
// trap into debugger (similar as done when PANIC occured)
|
|
bx_debug_break();
|
|
#endif
|
|
if (SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->get()) {
|
|
BX_ERROR(("exception(): 3rd (%d) exception with no resolution, shutdown status is %02xh, resetting", vector, DEV_cmos_get_reg(0x0f)));
|
|
bx_pc_system.Reset(BX_RESET_HARDWARE);
|
|
}
|
|
else {
|
|
BX_PANIC(("exception(): 3rd (%d) exception with no resolution", vector));
|
|
BX_ERROR(("WARNING: Any simulation after this point is completely bogus !"));
|
|
shutdown();
|
|
}
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|
|
}
|
|
|
|
// note: fault-class exceptions _except_ #DB set RF in
|
|
// eflags image.
|
|
if (exception_class == BX_EXCEPTION_CLASS_FAULT)
|
|
{
|
|
// restore RIP/RSP to value before error occurred
|
|
RIP = BX_CPU_THIS_PTR prev_rip;
|
|
if (BX_CPU_THIS_PTR speculative_rsp)
|
|
RSP = BX_CPU_THIS_PTR prev_rsp;
|
|
|
|
if (vector != BX_DB_EXCEPTION) BX_CPU_THIS_PTR assert_RF();
|
|
}
|
|
|
|
if (vector == BX_DB_EXCEPTION) {
|
|
// Commit debug events to DR6
|
|
#if BX_CPU_LEVEL <= 4
|
|
// On 386/486 bit12 is settable
|
|
BX_CPU_THIS_PTR dr6.val32 = (BX_CPU_THIS_PTR dr6.val32 & 0xffff0ff0) |
|
|
(BX_CPU_THIS_PTR debug_trap & 0x0000f00f);
|
|
#else
|
|
// On Pentium+, bit12 is always zero
|
|
BX_CPU_THIS_PTR dr6.val32 = (BX_CPU_THIS_PTR dr6.val32 & 0xffff0ff0) |
|
|
(BX_CPU_THIS_PTR debug_trap & 0x0000e00f);
|
|
#endif
|
|
// clear GD flag in the DR7 prior entering debug exception handler
|
|
BX_CPU_THIS_PTR dr7.set_GD(0);
|
|
}
|
|
|
|
BX_CPU_THIS_PTR EXT = 1;
|
|
|
|
/* if we've already had 1st exception, see if 2nd causes a
|
|
* Double Fault instead. Otherwise, just record 1st exception
|
|
*/
|
|
if (BX_CPU_THIS_PTR errorno > 0 && exception_type != BX_ET_DOUBLE_FAULT) {
|
|
if (! is_exception_OK[BX_CPU_THIS_PTR curr_exception][exception_type]) {
|
|
exception(BX_DF_EXCEPTION, 0);
|
|
}
|
|
}
|
|
|
|
BX_CPU_THIS_PTR curr_exception = exception_type;
|
|
BX_CPU_THIS_PTR errorno++;
|
|
|
|
if (real_mode()) {
|
|
push_error = 0; // not INT, no error code pushed
|
|
error_code = 0;
|
|
}
|
|
|
|
interrupt(vector, BX_HARDWARE_EXCEPTION, push_error, error_code);
|
|
BX_CPU_THIS_PTR errorno = 0; // error resolved
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|