524 lines
16 KiB
C++
524 lines
16 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011-2017 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "cpu.h"
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#include "param_names.h"
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#include "atom_n270.h"
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#define LOG_THIS cpu->
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#if BX_CPU_LEVEL >= 6
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atom_n270_t::atom_n270_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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{
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if (! BX_SUPPORT_MONITOR_MWAIT)
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BX_INFO(("WARNING: MONITOR/MWAIT support is not compiled in !"));
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enable_cpu_extension(BX_ISA_X87);
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enable_cpu_extension(BX_ISA_486);
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enable_cpu_extension(BX_ISA_PENTIUM);
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enable_cpu_extension(BX_ISA_MMX);
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enable_cpu_extension(BX_ISA_P6);
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enable_cpu_extension(BX_ISA_SYSENTER_SYSEXIT);
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enable_cpu_extension(BX_ISA_SSE);
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enable_cpu_extension(BX_ISA_SSE2);
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enable_cpu_extension(BX_ISA_SSE3);
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enable_cpu_extension(BX_ISA_SSSE3);
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#if BX_SUPPORT_MONITOR_MWAIT
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enable_cpu_extension(BX_ISA_MONITOR_MWAIT);
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#endif
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enable_cpu_extension(BX_ISA_CLFLUSH);
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enable_cpu_extension(BX_ISA_DEBUG_EXTENSIONS);
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enable_cpu_extension(BX_ISA_VME);
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enable_cpu_extension(BX_ISA_PSE);
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enable_cpu_extension(BX_ISA_PAE);
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enable_cpu_extension(BX_ISA_PGE);
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#if BX_PHY_ADDRESS_LONG
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enable_cpu_extension(BX_ISA_PSE36);
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#endif
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enable_cpu_extension(BX_ISA_MTRR);
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enable_cpu_extension(BX_ISA_PAT);
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enable_cpu_extension(BX_ISA_XAPIC);
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enable_cpu_extension(BX_ISA_MOVBE);
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}
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void atom_n270_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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{
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static const char* brand_string = " Intel(R) Atom(TM) CPU N270 @ 1.60GHz";
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static bx_bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
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if (cpuid_limit_winnt)
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if (function > 2 && function < 0x80000000) function = 2;
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switch(function) {
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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get_ext_cpuid_brand_string_leaf(brand_string, function, leaf);
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return;
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case 0x80000005:
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get_reserved_leaf(leaf);
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return;
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case 0x80000006:
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get_ext_cpuid_leaf_6(leaf);
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return;
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case 0x80000007:
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get_ext_cpuid_leaf_7(leaf);
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return;
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case 0x80000008:
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get_ext_cpuid_leaf_8(leaf);
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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case 0x00000002:
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get_std_cpuid_leaf_2(leaf);
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return;
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case 0x00000003:
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get_reserved_leaf(leaf);
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return;
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case 0x00000004:
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get_std_cpuid_leaf_4(subfunction, leaf);
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return;
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case 0x00000005:
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get_std_cpuid_leaf_5(leaf);
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return;
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case 0x00000006:
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get_std_cpuid_leaf_6(leaf);
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return;
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case 0x00000007:
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case 0x00000008:
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case 0x00000009:
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get_reserved_leaf(leaf);
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return;
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case 0x0000000A:
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default:
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get_std_cpuid_leaf_A(leaf);
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return;
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}
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}
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// leaf 0x00000000 //
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void atom_n270_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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// EAX: highest std function understood by CPUID
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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get_leaf_0(0xA, "GenuineIntel", leaf);
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}
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// leaf 0x00000001 //
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void atom_n270_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x000106C2;
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// EBX:
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// [7:0] Brand ID
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// [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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unsigned n_logical_processors = ncores*nthreads;
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leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8) |
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(n_logical_processors << 16);
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#if BX_SUPPORT_APIC
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leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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// * [0:0] SSE3: SSE3 Instructions
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// [1:1] PCLMULQDQ Instruction support
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// * [2:2] DTES64: 64-bit DS area
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// * [3:3] MONITOR/MWAIT support
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// * [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// * [7:7] EST: Enhanced Intel SpeedStep Technology
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// * [8:8] TM2: Thermal Monitor 2
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// * [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// * [14:14] xTPR update control
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// * [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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// [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// * [22:22] MOVBE instruction
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// [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// [25:25] AES Instructions
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [29:29] AVX F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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leaf->ecx = BX_CPUID_EXT_SSE3 |
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BX_CPUID_EXT_DTES64 |
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#if BX_SUPPORT_MONITOR_MWAIT
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BX_CPUID_EXT_MONITOR_MWAIT |
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#endif
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BX_CPUID_EXT_DS_CPL |
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BX_CPUID_EXT_EST |
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BX_CPUID_EXT_THERMAL_MONITOR2 |
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BX_CPUID_EXT_SSSE3 |
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BX_CPUID_EXT_xTPR |
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BX_CPUID_EXT_PDCM |
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BX_CPUID_EXT_MOVBE;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSENTER/SYSEXIT support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// - [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// * [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// * [21:21] DS: Debug Store
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// * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] SSE: SSE Extensions
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// * [26:26] SSE2: SSE2 Extensions
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// * [27:27] Self Snoop
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// * [28:28] Hyper Threading Technology
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// * [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// * [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD_SYSENTER_SYSEXIT |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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#if BX_PHY_ADDRESS_LONG
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BX_CPUID_STD_PSE36 |
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#endif
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BX_CPUID_STD_CLFLUSH |
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BX_CPUID_STD_DEBUG_STORE |
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BX_CPUID_STD_ACPI |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD_SSE |
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BX_CPUID_STD_SSE2 |
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BX_CPUID_STD_SELF_SNOOP |
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#if BX_SUPPORT_SMP
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BX_CPUID_STD_HT |
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#endif
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BX_CPUID_STD_THERMAL_MONITOR |
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BX_CPUID_STD_PBE;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x00000002 //
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void atom_n270_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000002 - Cache and TLB Descriptors
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leaf->eax = 0x4FBA5901;
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leaf->ebx = 0x0E3080C0;
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leaf->ecx = 0x00000000;
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leaf->edx = 0x00000000;
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}
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// leaf 0x00000003 - Processor Serial Number (not supported) //
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// leaf 0x00000004 //
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void atom_n270_t::get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000004 - Deterministic Cache Parameters
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// EAX:
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// [04-00] - Cache Type Field
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// 0 = No more caches
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// 1 = Data Cache
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// 2 = Instruction Cache
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// 3 = Unified Cache
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// [07-05] - Cache Level (starts at 1)]
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// [08] - Self Initializing cache level (doesn't need software initialization)
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// [09] - Fully Associative cache
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// [13-10] - Reserved
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// [25-14] - Maximum number of addressable IDs for logical processors sharing this cache
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// [31-26] - Maximum number of addressable IDs for processor cores in the physical package - 1
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// EBX:
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// [11-00] - L = System Coherency Line Size
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// [21-12] - P = Physical Line partitions
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// [31-22] - W = Ways of associativity
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// ECX: Number of Sets
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// EDX:
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// [00] - Writeback invalidate
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// [01] - Cache Inclusiveness
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// [02] - Complex Cache Indexing
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// [31-03] - Reserved
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switch(subfunction) {
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case 0:
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leaf->eax = 0x00004121;
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leaf->ebx = 0x0140003F;
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leaf->ecx = 0x0000003F;
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leaf->edx = 0x00000001;
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break;
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case 1:
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leaf->eax = 0x00004122;
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leaf->ebx = 0x01C0003F;
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leaf->ecx = 0x0000003F;
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leaf->edx = 0x00000001;
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break;
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case 2:
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leaf->eax = 0x00004143;
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leaf->ebx = 0x01C0003F;
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leaf->ecx = 0x000003FF;
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leaf->edx = 0x00000001;
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break;
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default:
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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return;
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}
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}
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// leaf 0x00000005 //
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void atom_n270_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000005 - MONITOR/MWAIT Leaf
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#if BX_SUPPORT_MONITOR_MWAIT
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// EAX - Smallest monitor-line size in bytes
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// EBX - Largest monitor-line size in bytes
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// ECX -
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// [31:2] - reserved
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// [1:1] - exit MWAIT even with EFLAGS.IF = 0
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// [0:0] - MONITOR/MWAIT extensions are supported
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// EDX -
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// [03-00] - number of C0 sub C-states supported using MWAIT
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// [07-04] - number of C1 sub C-states supported using MWAIT
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// [11-08] - number of C2 sub C-states supported using MWAIT
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// [15-12] - number of C3 sub C-states supported using MWAIT
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// [19-16] - number of C4 sub C-states supported using MWAIT
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// [31-20] - reserved (MBZ)
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leaf->eax = CACHE_LINE_SIZE;
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leaf->ebx = CACHE_LINE_SIZE;
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leaf->ecx = 3;
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leaf->edx = 0x00020220;
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#else
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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#endif
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}
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// leaf 0x00000006 //
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void atom_n270_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000006 - Thermal and Power Management Leaf
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leaf->eax = 0x00000001;
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leaf->ebx = 0x00000002;
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leaf->ecx = 0x00000001;
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leaf->edx = 0x00000000;
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}
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// leaf 0x00000007 not supported //
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// leaf 0x00000008 reserved //
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// leaf 0x00000009 direct cache access not supported //
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// leaf 0x0000000A //
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void atom_n270_t::get_std_cpuid_leaf_A(cpuid_function_t *leaf) const
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{
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// CPUID function 0x0000000A - Architectural Performance Monitoring Leaf
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// EAX:
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// [7:0] Version ID of architectural performance monitoring
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// [15:8] Number of general-purpose performance monitoring counters per logical processor
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// [23:16] Bit width of general-purpose, performance monitoring counter
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// [31:24] Length of EBX bit vector to enumerate architectural performance
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// monitoring events.
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// EBX:
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// [0] Core cycle event not available if 1
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// [1] Instruction retired event not available if 1
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// [2] Reference cycles event not available if 1
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// [3] Last-level cache reference event not available if 1
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// [4] Last-level cache misses event not available if 1
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// [5] Branch instruction retired event not available if 1
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// [6] Branch mispredict retired event not available if 1
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// [31:7] reserved
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// ECX: reserved
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// EDX:
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// [4:0] Number of fixed performance counters (if Version ID > 1)
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// [12:5] Bit width of fixed-function performance counters (if Version ID > 1)
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// [31:13] reserved
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leaf->eax = 0x07280203;
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leaf->ebx = 0x00000000;
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leaf->ecx = 0x00000000;
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leaf->edx = 0x00002501;
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BX_INFO(("WARNING: Architectural Performance Monitoring is not implemented"));
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}
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// leaf 0x80000000 //
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void atom_n270_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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// EAX: highest extended function understood by CPUID
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// EBX: reserved
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// EDX: reserved
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// ECX: reserved
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get_leaf_0(0x80000008, NULL, leaf);
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}
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// leaf 0x80000001 //
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void atom_n270_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information (reserved for Intel)
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leaf->eax = 0;
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// EBX: Brand ID (reserved for Intel)
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leaf->ebx = 0;
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// ECX:
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// ? [0:0] LAHF/SAHF instructions support in 64-bit mode
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// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
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// [2:2] SVM: Secure Virtual Machine (AMD)
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// [3:3] Extended APIC Space
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// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
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// [5:5] LZCNT: LZCNT instruction support
|
|
// [6:6] SSE4A: SSE4A Instructions support
|
|
// [7:7] Misaligned SSE support
|
|
// [8:8] PREFETCHW: PREFETCHW instruction support
|
|
// [9:9] OSVW: OS visible workarounds (AMD)
|
|
// [11:10] reserved
|
|
// [12:12] SKINIT support
|
|
// [13:13] WDT: Watchdog timer support
|
|
// [31:14] reserved
|
|
|
|
leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF;
|
|
|
|
// EDX:
|
|
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
|
|
// [10:0] Reserved for Intel
|
|
// [11:11] SYSCALL/SYSRET support
|
|
// [19:12] Reserved for Intel
|
|
// [20:20] No-Execute page protection
|
|
// [25:21] Reserved
|
|
// [26:26] 1G paging support
|
|
// [27:27] Support RDTSCP Instruction
|
|
// [28:28] Reserved
|
|
// [29:29] Long Mode
|
|
// [30:30] AMD 3DNow! Extensions
|
|
// [31:31] AMD 3DNow! Instructions
|
|
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
// leaf 0x80000002 //
|
|
// leaf 0x80000003 //
|
|
// leaf 0x80000004 //
|
|
|
|
// leaf 0x80000005 - L1 Cache and TLB Identifiers (reserved for Intel)
|
|
|
|
// leaf 0x80000006 //
|
|
void atom_n270_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000006 - L2 Cache and TLB Identifiers
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00000000;
|
|
leaf->ecx = 0x02008040;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x80000007 //
|
|
void atom_n270_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000007 - Advanced Power Management
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
// leaf 0x80000008 //
|
|
|
|
void atom_n270_t::dump_cpuid(void) const
|
|
{
|
|
bx_cpuid_t::dump_cpuid(0xA, 0x8);
|
|
}
|
|
|
|
bx_cpuid_t *create_atom_n270_cpuid(BX_CPU_C *cpu) { return new atom_n270_t(cpu); }
|
|
|
|
#endif
|