1452 lines
50 KiB
C++
1452 lines
50 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.76 2006-06-17 12:09:55 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// Notes from merge of x86-64 enhancements:
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// Looks like for x86-64/PAE=1/PTE with PSE=1, the
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// CR4.PSE field is not consulted by the processor?
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// Fix the PAE case to not update the page table tree entries
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// until the final protection check? This is how it is on
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// P6 for non-PAE anyways...
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if 0
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// X86 Registers Which Affect Paging:
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// ==================================
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//
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// CR0:
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// bit 31: PG, Paging (386+)
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// bit 16: WP, Write Protect (486+)
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// 0: allow supervisor level writes into user level RO pages
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// 1: inhibit supervisor level writes into user level RO pages
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//
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// CR3:
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// bit 31..12: PDBR, Page Directory Base Register (386+)
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// bit 4: PCD, Page level Cache Disable (486+)
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// Controls caching of current page directory. Affects only the processor's
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// internal caches (L1 and L2).
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// This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
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// Values:
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// 0: Page Directory can be cached
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// 1: Page Directory not cached
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// bit 3: PWT, Page level Writes Transparent (486+)
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// Controls write-through or write-back caching policy of current page
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// directory. Affects only the processor's internal caches (L1 and L2).
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// This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
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// Values:
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// 0: write-back caching enabled
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// 1: write-through caching enabled
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//
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// CR4:
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// bit 4: PSE, Page Size Extension (Pentium+)
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// 0: 4KByte pages (typical)
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// 1: 4MByte or 2MByte pages
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// bit 5: PAE, Physical Address Extension (Pentium Pro+)
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// 0: 32bit physical addresses
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// 1: 36bit physical addresses
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// bit 7: PGE, Page Global Enable (Pentium Pro+)
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// The global page feature allows frequently used or shared pages
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// to be marked as global (PDE or PTE bit 8). Global pages are
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// not flushed from TLB on a task switch or write to CR3.
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// Values:
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// 0: disables global page feature
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// 1: enables global page feature
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//
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// Page size extention and physical address size extention matrix
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// ====================================================================
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// CR0.PG CR4.PAE CR4.PSE PDE.PS | page size physical address size
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// ====================================================================
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// 0 X X X | - paging disabled
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// 1 0 0 X | 4K 32bits
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// 1 0 1 0 | 4K 32bits
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// 1 0 1 1 | 4M 32bits
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// 1 1 X 0 | 4K 36bits
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// 1 1 X 1 | 2M 36bits
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// Page Directory/Table Entry format when P=0:
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// ===========================================
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//
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// 31.. 1: available
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// 0: P=0
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// Page Directory Entry format when P=1 (4-Kbyte Page Table):
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// ==========================================================
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//
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// 31..12: page table base address
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// 11.. 9: available
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// 8: G (Pentium Pro+), 0=reserved otherwise
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// 7: PS (Pentium+), 0=reserved otherwise
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// 6: 0=reserved
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// 5: A (386+)
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// 4: PCD (486+), 0=reserved otherwise
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// 3: PWT (486+), 0=reserved otherwise
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// 2: U/S (386+)
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// 1: R/W (386+)
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// 0: P=1 (386+)
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// Page Table Entry format when P=1 (4-Kbyte Page):
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// ================================================
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//
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// 63..63: NX |
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// 62..52: available | Long mode
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// 51..32: page base address |
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// 31..12: page base address
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// 11.. 9: available
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// 8: G (Pentium Pro+), 0=reserved otherwise
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// 7: PAT
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// 6: D (386+)
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// 5: A (386+)
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// 4: PCD (486+), 0=reserved otherwise
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// 3: PWT (486+), 0=reserved otherwise
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// 2: U/S (386+)
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// 1: R/W (386+)
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// 0: P=1 (386+)
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// Page Directory/Table Entry Fields Defined:
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// ==========================================
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// NX: No Execute
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// This bit controls the ability to execute code from all physical
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// pages mapped by the table entry.
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// 0: Code can be executed from the mapped physical pages
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// 1: Code cannot be executed
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// The NX bit can only be set when the no-execute page-protection
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// feature is enabled by setting EFER.NXE=1, If EFER.NXE=0, the
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// NX bit is treated as reserved. In this case, #PF occurs if the
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// NX bit is not cleared to zero.
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//
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// G: Global flag
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// Indiciates a global page when set. When a page is marked
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// global and the PGE flag in CR4 is set, the page table or
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// directory entry for the page is not invalidated in the TLB
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// when CR3 is loaded or a task switch occurs. Only software
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// clears and sets this flag. For page directory entries that
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// point to page tables, this flag is ignored and the global
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// characteristics of a page are set in the page table entries.
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//
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// PS: Page Size flag
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// Only used in page directory entries. When PS=0, the page
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// size is 4KBytes and the page directory entry points to a
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// page table. When PS=1, the page size is 4MBytes for
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// normal 32-bit addressing and 2MBytes if extended physical
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// addressing.
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//
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// PAT: Page-Attribute Table
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// This bit is only present in the lowest level of the page
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// translation hierarchy. The PAT bit is the high-order bit
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// of a 3-bit index into the PAT register. The other two
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// bits involved in forming the index are the PCD and PWT
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// bits.
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//
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// D: Dirty bit:
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// Processor sets the Dirty bit in the 2nd-level page table before a
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// write operation to an address mapped by that page table entry.
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// Dirty bit in directory entries is undefined.
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//
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// A: Accessed bit:
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// Processor sets the Accessed bits in both levels of page tables before
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// a read/write operation to a page.
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//
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// PCD: Page level Cache Disable
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// Controls caching of individual pages or page tables.
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// This allows a per-page based mechanism to disable caching, for
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// those pages which contained memory mapped IO, or otherwise
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// should not be cached. Processor ignores this flag if paging
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// is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
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// Values:
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// 0: page or page table can be cached
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// 1: page or page table is not cached (prevented)
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//
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// PWT: Page level Write Through
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// Controls the write-through or write-back caching policy of individual
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// pages or page tables. Processor ignores this flag if paging
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// is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
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// Values:
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// 0: write-back caching
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// 1: write-through caching
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//
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// U/S: User/Supervisor level
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// 0: Supervisor level - for the OS, drivers, etc.
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// 1: User level - application code and data
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//
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// R/W: Read/Write access
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// 0: read-only access
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// 1: read/write access
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//
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// P: Present
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// 0: Not present
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// 1: Present
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// ==========================================
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// Combined page directory/page table protection:
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// ==============================================
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// There is one column for the combined effect on a 386
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// and one column for the combined effect on a 486+ CPU.
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//
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// +----------------+-----------------+----------------+----------------+
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// | Page Directory| Page Table | Combined 386 | Combined 486+ |
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// |Privilege Type | Privilege Type | Privilege Type| Privilege Type|
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// |----------------+-----------------+----------------+----------------|
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// |User R | User R | User R | User R |
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// |User R | User RW | User R | User R |
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// |User RW | User R | User R | User R |
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// |User RW | User RW | User RW | User RW |
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// |User R | Supervisor R | User R | Supervisor RW |
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// |User R | Supervisor RW | User R | Supervisor RW |
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// |User RW | Supervisor R | User R | Supervisor RW |
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// |User RW | Supervisor RW | User RW | Supervisor RW |
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// |Supervisor R | User R | User R | Supervisor RW |
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// |Supervisor R | User RW | User R | Supervisor RW |
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// |Supervisor RW | User R | User R | Supervisor RW |
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// |Supervisor RW | User RW | User RW | Supervisor RW |
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// |Supervisor R | Supervisor R | Supervisor RW | Supervisor RW |
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// |Supervisor R | Supervisor RW | Supervisor RW | Supervisor RW |
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// |Supervisor RW | Supervisor R | Supervisor RW | Supervisor RW |
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// |Supervisor RW | Supervisor RW | Supervisor RW | Supervisor RW |
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// +----------------+-----------------+----------------+----------------+
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// Page Fault Error Code Format:
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// =============================
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//
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// bits 31..4: Reserved
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// bit 3: RSVD (Pentium Pro+)
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// 0: fault caused by reserved bits set to 1 in a page directory
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// when the PSE or PAE flags in CR4 are set to 1
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// 1: fault was not caused by reserved bit violation
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// bit 2: U/S (386+)
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// 0: fault originated when in supervior mode
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// 1: fault originated when in user mode
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// bit 1: R/W (386+)
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// 0: access causing the fault was a read
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// 1: access causing the fault was a write
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// bit 0: P (386+)
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// 0: fault caused by a nonpresent page
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// 1: fault caused by a page level protection violation
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// Some paging related notes:
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// ==========================
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//
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// - When the processor is running in supervisor level, all pages are both
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// readable and writable (write-protect ignored). When running at user
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// level, only pages which belong to the user level are accessible;
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// read/write & read-only are readable, read/write are writable.
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//
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// - If the Present bit is 0 in either level of page table, an
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// access which uses these entries will generate a page fault.
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//
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// - (A)ccess bit is used to report read or write access to a page
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// or 2nd level page table.
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//
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// - (D)irty bit is used to report write access to a page.
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//
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// - Processor running at CPL=0,1,2 maps to U/S=0
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// Processor running at CPL=3 maps to U/S=1
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//
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// - Pentium+ processors have separate TLB's for data and instruction caches
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// - Pentium Pro+ processors maintain separate 4K and 4M TLBs.
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#endif
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#if BX_SUPPORT_PAGING
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#define BX_INVALID_TLB_ENTRY 0xffffffff
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#if BX_USE_QUICK_TLB_INVALIDATE
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#define BX_MAX_TLB_INVALIDATE 0xffe
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#endif
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#define BX_USE_TLB_GENERATION 1
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#if BX_CPU_LEVEL >= 4
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# define BX_PRIV_CHECK_SIZE 32
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#else
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# define BX_PRIV_CHECK_SIZE 16
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#endif
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// The 'priv_check' array is used to decide if the current access
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// has the proper paging permissions. An index is formed, based
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// on parameters such as the access type and level, the write protect
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// flag and values cached in the TLB. The format of the index into this
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// array is:
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//
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// |4 |3 |2 |1 |0 |
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// |wp|us|us|rw|rw|
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// | | | | |
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// | | | | +---> r/w of current access
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// | | +--+------> u/s,r/w combined of page dir & table (cached)
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// | +------------> u/s of current access
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// +---------------> Current CR0.wp value
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// Each entry in the TLB cache has 3 entries:
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// lpf: Linear Page Frame (page aligned linear address of page)
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// bits 32..12 Linear page frame.
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// bits 11..0 Invalidate index.
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// ppf: Physical Page Frame (page aligned phy address of page)
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// accessBits:
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// bits 32..11: Host Page Frame address used for direct access to
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// the mem.vector[] space allocated for the guest physical
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// memory. If this is zero, it means that a pointer
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// to the host space could not be generated, likely because
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// that page of memory is not standard memory (it might
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// be memory mapped IO, ROM, etc).
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// bits 9..10: (currently unused)
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//
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// bit 8: Page is a global page.
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//
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//
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// The following 4 bits are used for a very efficient permissions
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// check. The goal is to be able, using only the current privilege
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// level and access type, to determine if the page tables allow the
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// access to occur or at least should rewalk the page tables. On
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// the first read access, permissions are set to only read, so a
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// rewalk is necessary when a subsequent write fails the tests.
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// This allows for the dirty bit to be set properly, but for the
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// test to be efficient. Note that the CR0.WP flag is not present.
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// The values in the following flags is based on the current CR0.WP
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// value, necessitating a TLB flush when CR0.WP changes.
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//
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// The test is:
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// OK = 0x1 << ( (W<<1) | U ) [W:1=write, 0=read, U:1=CPL3,0=CPL0-2]
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//
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// Thus for reads, it is:
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// OK = 0x1 << ( U )
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// And for writes:
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// OK = 0x4 << ( U )
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//
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// bit 7: a Write from User privilege is OK
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// bit 6: a Write from System privilege is OK
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// bit 5: a Read from User privilege is OK
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// bit 4: a Read from System privilege is OK
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//
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// And the lowest 4 bits are as above, except that they also indicate
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// that hostPageAddr is valid, so we do not separately need to test
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// that pointer against NULL. These have smaller constants for us
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// to be able to use smaller encodings in the trace generators. Note
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// that whenever bit n (n=0,1,2,3) is set, then also n+4 is set.
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// (The opposite is of course not true)
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//
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// bit 3: a Write from User privilege is OK, hostPageAddr is valid
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// bit 2: a Write from System privilege is OK, hostPageAddr is valid
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// bit 1: a Read from User privilege is OK, hostPageAddr is valid
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// bit 0: a Read from System privilege is OK, hostPageAddr is valid
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//
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#define TLB_GlobalPage 0x100
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#define TLB_WriteUserOK 0x80
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#define TLB_WriteSysOK 0x40
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#define TLB_ReadUserOK 0x20
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#define TLB_ReadSysOK 0x10
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#define TLB_WriteUserPtrOK 0x08
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#define TLB_WriteSysPtrOK 0x04
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#define TLB_ReadUserPtrOK 0x02
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#define TLB_ReadSysPtrOK 0x01
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#ifdef __GNUC__
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#warning "Move priv_check to CPU fields, or init.cc"
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#endif
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static unsigned priv_check[BX_PRIV_CHECK_SIZE];
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#define PAGE_DIRECTORY_NX_BIT (BX_CONST64(0x8000000000000000))
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// === TLB Instrumentation section ==============================
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// Note: this is an approximation of what Peter Tattam had.
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#define InstrumentTLB 0
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#if InstrumentTLB
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static unsigned tlbLookups=0;
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static unsigned tlbMisses=0;
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static unsigned tlbGlobalFlushes=0;
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static unsigned tlbNonGlobalFlushes=0;
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static unsigned tlbEntryFlushes=0;
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static unsigned tlbEntryInvlpg=0;
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#define InstrTLB_StatsMask 0xfffff
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#define InstrTLB_Stats() {\
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if ((tlbLookups & InstrTLB_StatsMask) == 0) { \
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BX_INFO(("TLB lookup:%8d miss:%8d %6.2f%% flush:%8d %6.2f%%", \
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tlbLookups, \
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tlbMisses, \
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tlbMisses * 100.0 / tlbLookups, \
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(tlbGlobalFlushes+tlbNonGlobalFlushes), \
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(tlbGlobalFlushes+tlbNonGlobalFlushes) * 100.0 / tlbLookups \
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)); \
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tlbLookups = tlbMisses = tlbGlobalFlushes = tlbNonGlobalFlushes = 0; \
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} \
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}
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#define InstrTLB_Increment(v) (v)++
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#else
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#define InstrTLB_Stats()
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#define InstrTLB_Increment(v)
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#endif
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// ==============================================================
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::pagingCR0Changed(Bit32u oldCR0, Bit32u newCR0)
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{
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// Modification of PG,PE flushes TLB cache according to docs.
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// Additionally, the TLB strategy is based on the current value of
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// WP, so if that changes we must also flush the TLB.
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if ( (oldCR0 & 0x80010001) != (newCR0 & 0x80010001) )
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TLB_flush(1); // 1 = Flush Global entries also.
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if (bx_dbg.paging)
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BX_INFO(("pagingCR0Changed: (0x%x -> 0x%x)", oldCR0, newCR0));
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}
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::pagingCR4Changed(Bit32u oldCR4, Bit32u newCR4)
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{
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// Modification of PGE,PAE,PSE flushes TLB cache according to docs.
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if ((oldCR4 & 0x000000b0) != (newCR4 & 0x000000b0))
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TLB_flush(1); // 1 = Flush Global entries also.
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if (bx_dbg.paging)
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BX_INFO(("pagingCR4Changed: (0x%x -> 0x%x)", oldCR4, newCR4));
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#if BX_SUPPORT_PAE
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if ((oldCR4 & 0x00000020) != (newCR4 & 0x00000020)) {
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if (BX_CPU_THIS_PTR cr4.get_PAE())
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BX_CPU_THIS_PTR cr3_masked = BX_CPU_THIS_PTR cr3 & 0xffffffe0;
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else
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BX_CPU_THIS_PTR cr3_masked = BX_CPU_THIS_PTR cr3 & 0xfffff000;
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}
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#endif
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}
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void BX_CPP_AttrRegparmN(1)
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BX_CPU_C::CR3_change(bx_phy_address value)
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{
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if (bx_dbg.paging) {
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BX_INFO(("CR3_change(): flush TLB cache"));
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BX_INFO(("Page Directory Base %08x", (unsigned) value));
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}
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|
|
// flush TLB even if value does not change
|
|
TLB_flush(0); // 0 = Don't flush Global entries.
|
|
BX_CPU_THIS_PTR cr3 = value;
|
|
#if BX_SUPPORT_PAE
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE())
|
|
BX_CPU_THIS_PTR cr3_masked = value & 0xffffffe0;
|
|
else
|
|
#endif
|
|
BX_CPU_THIS_PTR cr3_masked = value & 0xfffff000;
|
|
}
|
|
|
|
void BX_CPU_C::TLB_init(void)
|
|
{
|
|
// Called to initialize the TLB upon startup.
|
|
// Unconditional initialization of all TLB entries.
|
|
|
|
#if BX_USE_TLB
|
|
unsigned i;
|
|
unsigned wp, us_combined, rw_combined, us_current, rw_current;
|
|
|
|
for (i=0; i<BX_TLB_SIZE; i++)
|
|
BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
|
|
|
|
//
|
|
// Setup privilege check matrix.
|
|
//
|
|
|
|
for (i=0; i<BX_PRIV_CHECK_SIZE; i++) {
|
|
wp = (i & 0x10) >> 4;
|
|
us_current = (i & 0x08) >> 3;
|
|
us_combined = (i & 0x04) >> 2;
|
|
rw_combined = (i & 0x02) >> 1;
|
|
rw_current = (i & 0x01) >> 0;
|
|
if (wp) { // when write protect on
|
|
if (us_current > us_combined) // user access, supervisor page
|
|
priv_check[i] = 0;
|
|
else if (rw_current > rw_combined) // RW access, RO page
|
|
priv_check[i] = 0;
|
|
else
|
|
priv_check[i] = 1;
|
|
}
|
|
else { // when write protect off
|
|
if (us_current == 0) // Supervisor mode access, anything goes
|
|
priv_check[i] = 1;
|
|
else {
|
|
// user mode access
|
|
if (us_combined == 0) // user access, supervisor Page
|
|
priv_check[i] = 0;
|
|
else if (rw_current > rw_combined) // RW access, RO page
|
|
priv_check[i] = 0;
|
|
else
|
|
priv_check[i] = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
#if BX_USE_QUICK_TLB_INVALIDATE
|
|
BX_CPU_THIS_PTR TLB.tlb_invalidate = BX_MAX_TLB_INVALIDATE;
|
|
#endif
|
|
|
|
#endif // #if BX_USE_TLB
|
|
}
|
|
|
|
void BX_CPU_C::TLB_flush(bx_bool invalidateGlobal)
|
|
{
|
|
#if InstrumentTLB
|
|
if (invalidateGlobal)
|
|
InstrTLB_Increment(tlbGlobalFlushes);
|
|
else
|
|
InstrTLB_Increment(tlbNonGlobalFlushes);
|
|
#endif
|
|
|
|
#if BX_USE_TLB
|
|
for (unsigned i=0; i<BX_TLB_SIZE; i++) {
|
|
// To be conscious of the native cache line usage, only
|
|
// write to (invalidate) entries which need it.
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[i];
|
|
if (tlbEntry->lpf != BX_INVALID_TLB_ENTRY) {
|
|
#if BX_SUPPORT_GLOBAL_PAGES
|
|
if (invalidateGlobal || !(tlbEntry->accessBits & TLB_GlobalPage))
|
|
#endif
|
|
{
|
|
tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
|
|
InstrTLB_Increment(tlbEntryFlushes); // A TLB entry flush occurred.
|
|
}
|
|
}
|
|
}
|
|
#endif // #if BX_USE_TLB
|
|
}
|
|
|
|
void BX_CPU_C::TLB_invlpg(bx_address laddr)
|
|
{
|
|
Bit32u TLB_index = BX_TLB_INDEX_OF(laddr);
|
|
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
|
|
InstrTLB_Increment(tlbEntryFlushes); // A TLB entry flush occurred.
|
|
}
|
|
|
|
void BX_CPU_C::INVLPG(bxInstruction_c* i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 4
|
|
invalidate_prefetch_q();
|
|
|
|
if (i->modC0()) {
|
|
BX_INFO(("INVLPG: op is a register"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
// Can not be executed in v8086 mode
|
|
if (v8086_mode()) {
|
|
BX_ERROR(("INVLPG: cannot be executed in v8086 mode"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
// Protected instruction: CPL0 only
|
|
if (BX_CPU_THIS_PTR cr0.pe) {
|
|
if (CPL!=0) {
|
|
BX_ERROR(("INVLPG: #GP(0) in protected mode with CPL != 0"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
|
|
#if BX_USE_TLB
|
|
bx_address laddr = BX_CPU_THIS_PTR get_segment_base(i->seg()) + RMAddr(i);
|
|
TLB_invlpg(laddr);
|
|
InstrTLB_Increment(tlbEntryInvlpg);
|
|
#endif // BX_USE_TLB
|
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_INVLPG, 0);
|
|
|
|
#else
|
|
// not supported on < 486
|
|
BX_INFO(("INVLPG: required i486, use --enable-cpu=4 option"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
// Translate a linear address to a physical address, for
|
|
// a data access (D)
|
|
|
|
bx_phy_address BX_CPP_AttrRegparmN(3)
|
|
BX_CPU_C::translate_linear(bx_address laddr, unsigned pl, unsigned rw, unsigned access_type)
|
|
{
|
|
bx_address lpf;
|
|
Bit32u accessBits, combined_access = 0, error_code = 0;
|
|
unsigned priv_index;
|
|
#if BX_USE_TLB
|
|
Bit32u TLB_index;
|
|
#endif
|
|
|
|
InstrTLB_Increment(tlbLookups);
|
|
InstrTLB_Stats();
|
|
|
|
// note - we assume physical memory < 4gig so for brevity & speed, we'll use
|
|
// 32 bit entries although cr3 is expanded to 64 bits.
|
|
Bit32u ppf, poffset;
|
|
bx_phy_address paddress;
|
|
|
|
bx_bool isWrite = (rw >= BX_WRITE); // write or r-m-w
|
|
|
|
#if BX_SUPPORT_PAE
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE())
|
|
{
|
|
bx_address pde, pdp;
|
|
bx_phy_address pde_addr;
|
|
bx_phy_address pdp_addr;
|
|
|
|
lpf = laddr & BX_CONST64(0xfffffffffffff000); // linear page frame
|
|
poffset = laddr & 0x00000fff; // physical offset
|
|
|
|
#if BX_USE_TLB
|
|
TLB_index = BX_TLB_INDEX_OF(lpf);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
|
|
|
|
if (tlbEntry->lpf == BX_TLB_LPF_VALUE(lpf))
|
|
{
|
|
paddress = tlbEntry->ppf | poffset;
|
|
accessBits = tlbEntry->accessBits;
|
|
|
|
if (accessBits & (0x10 << ((isWrite<<1) | pl)))
|
|
return(paddress);
|
|
|
|
// The current access does not have permission according to the info
|
|
// in our TLB cache entry. Re-walk the page tables, in case there is
|
|
// updated information in the memory image, and let the long path code
|
|
// generate an exception if one is warranted.
|
|
}
|
|
#endif
|
|
|
|
InstrTLB_Increment(tlbMisses);
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR msr.lma)
|
|
{
|
|
Bit64u pml4;
|
|
|
|
// Get PML4 entry
|
|
bx_phy_address pml4_addr = BX_CPU_THIS_PTR cr3_masked |
|
|
((laddr & BX_CONST64(0x0000ff8000000000)) >> 36);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pml4_addr, 8, &pml4);
|
|
|
|
if ( !(pml4 & 0x01) ) {
|
|
goto page_fault_not_present; // PML4 Entry NOT present
|
|
}
|
|
if (pml4 & PAGE_DIRECTORY_NX_BIT) {
|
|
if (! BX_CPU_THIS_PTR msr.nxe)
|
|
goto page_fault_reserved;
|
|
else if (access_type == CODE_ACCESS)
|
|
goto page_fault_access;
|
|
}
|
|
if ( !(pml4 & 0x20) )
|
|
{
|
|
pml4 |= 0x20;
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pml4_addr, 8, &pml4);
|
|
}
|
|
|
|
// Get PDP entry
|
|
pdp_addr = (pml4 & 0xfffff000) |
|
|
((laddr & BX_CONST64(0x0000007fc0000000)) >> 27);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
pdp_addr = BX_CPU_THIS_PTR cr3_masked | ((laddr & 0xc0000000) >> 27);
|
|
}
|
|
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pdp_addr, sizeof(bx_address), &pdp);
|
|
|
|
if ( !(pdp & 0x01) ) {
|
|
goto page_fault_not_present; // PDP Entry NOT present
|
|
}
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR msr.lma)
|
|
{
|
|
if (pdp & PAGE_DIRECTORY_NX_BIT) {
|
|
if (! BX_CPU_THIS_PTR msr.nxe)
|
|
goto page_fault_reserved;
|
|
else if (access_type == CODE_ACCESS)
|
|
goto page_fault_access;
|
|
}
|
|
}
|
|
#endif
|
|
if ( !(pdp & 0x20) ) {
|
|
pdp |= 0x20;
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pdp_addr, sizeof(bx_address), &pdp);
|
|
}
|
|
|
|
// Get page dir entry
|
|
pde_addr = (pdp & 0xfffff000) | ((laddr & 0x3fe00000) >> 18);
|
|
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pde_addr, sizeof(bx_address), &pde);
|
|
|
|
if ( !(pde & 0x01) ) {
|
|
goto page_fault_not_present; // Page Directory Entry NOT present
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (pde & PAGE_DIRECTORY_NX_BIT) {
|
|
if (! BX_CPU_THIS_PTR msr.nxe)
|
|
goto page_fault_reserved;
|
|
else if (access_type == CODE_ACCESS)
|
|
goto page_fault_access;
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_4MEG_PAGES
|
|
// (KPL) Weird. I would think the processor would consult CR.PSE?
|
|
// if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4.get_PSE())) {}
|
|
if (pde & 0x80) {
|
|
// 4M pages are enabled, and this is a 4Meg page.
|
|
|
|
// Combined access is just access from the pde (no pte involved).
|
|
combined_access = pde & 0x06; // U/S and R/W
|
|
// Make up the physical page frame address.
|
|
ppf = (pde & 0xffe00000) | (laddr & 0x001ff000);
|
|
|
|
#if BX_SUPPORT_GLOBAL_PAGES
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE()) { // PGE==1
|
|
combined_access |= (pde & TLB_GlobalPage); // G
|
|
}
|
|
#endif
|
|
|
|
priv_index =
|
|
#if BX_CPU_LEVEL >= 4
|
|
(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
|
|
#endif
|
|
(pl<<3) | // bit 3
|
|
(combined_access & 0x06) | // bit 2,1
|
|
isWrite; // bit 0
|
|
|
|
if (!priv_check[priv_index]) goto page_fault_access;
|
|
|
|
// Update PDE if A/D bits if needed.
|
|
if ( ((pde & 0x20)==0) || (isWrite && ((pde&0x40)==0)) )
|
|
{
|
|
pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pde_addr, sizeof(bx_address), &pde);
|
|
}
|
|
}
|
|
else
|
|
#endif
|
|
{ // 4k pages.
|
|
bx_address pte;
|
|
|
|
// Get page table entry
|
|
bx_phy_address pte_addr = (pde & 0xfffff000) | ((laddr & 0x001ff000) >> 9);
|
|
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pte_addr, sizeof(bx_address), &pte);
|
|
|
|
if ( !(pte & 0x01) ) {
|
|
goto page_fault_not_present;
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (pte & PAGE_DIRECTORY_NX_BIT) {
|
|
if (! BX_CPU_THIS_PTR msr.nxe)
|
|
goto page_fault_reserved;
|
|
else if (access_type == CODE_ACCESS)
|
|
goto page_fault_access;
|
|
}
|
|
#endif
|
|
|
|
combined_access = (pde & pte) & 0x06; // U/S and R/W
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = pte & 0xfffff000;
|
|
|
|
#if BX_SUPPORT_GLOBAL_PAGES
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE()) { // PGE==1
|
|
combined_access |= (pte & TLB_GlobalPage); // G
|
|
}
|
|
#endif
|
|
|
|
priv_index =
|
|
#if BX_CPU_LEVEL >= 4
|
|
(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
|
|
#endif
|
|
(pl<<3) | // bit 3
|
|
(combined_access & 0x06) | // bit 2,1
|
|
isWrite; // bit 0
|
|
|
|
if (!priv_check[priv_index]) goto page_fault_access;
|
|
|
|
// Update PDE A bit if needed.
|
|
if ( (pde & 0x20)==0 ) {
|
|
pde |= 0x20; // Update A bit.
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pde_addr, sizeof(bx_address), &pde);
|
|
}
|
|
|
|
// Update PTE A/D bits if needed.
|
|
if (((pte & 0x20)==0) || (isWrite && ((pte&0x40)==0)))
|
|
{
|
|
pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pte_addr, sizeof(bx_address), &pte);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
#endif // #if BX_SUPPORT_PAE
|
|
{
|
|
// CR4.PAE==0 (and MSR.LMA==0)
|
|
|
|
lpf = laddr & 0xfffff000; // linear page frame
|
|
poffset = laddr & 0x00000fff; // physical offset
|
|
|
|
#if BX_USE_TLB
|
|
TLB_index = BX_TLB_INDEX_OF(lpf);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
|
|
|
|
if (tlbEntry->lpf == BX_TLB_LPF_VALUE(lpf))
|
|
{
|
|
paddress = tlbEntry->ppf | poffset;
|
|
accessBits = tlbEntry->accessBits;
|
|
|
|
if (accessBits & (0x10 << ((isWrite<<1) | pl)))
|
|
return(paddress);
|
|
|
|
// The current access does not have permission according to the info
|
|
// in our TLB cache entry. Re-walk the page tables, in case there is
|
|
// updated information in the memory image, and let the long path code
|
|
// generate an exception if one is warranted.
|
|
}
|
|
#endif
|
|
|
|
InstrTLB_Increment(tlbMisses);
|
|
|
|
Bit32u pde;
|
|
bx_phy_address pde_addr;
|
|
|
|
// Get page dir entry
|
|
pde_addr = BX_CPU_THIS_PTR cr3_masked | ((laddr & 0xffc00000) >> 20);
|
|
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pde_addr, 4, &pde);
|
|
|
|
if ( !(pde & 0x01) ) {
|
|
goto page_fault_not_present; // Page Directory Entry NOT present
|
|
}
|
|
|
|
#if BX_SUPPORT_4MEG_PAGES
|
|
if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4.get_PSE()))
|
|
{
|
|
// 4M pages are enabled, and this is a 4Meg page.
|
|
// Note: when the PSE and PAE flags in CR4 are set,
|
|
// the processor generates a PF if the reserved bits are not
|
|
// set to 0. (We don't handle PAE yet, just a note for
|
|
// the future).
|
|
|
|
// Combined access is just access from the pde (no pte involved).
|
|
combined_access = pde & 0x006; // {US,RW}
|
|
// make up the physical frame number
|
|
ppf = (pde & 0xFFC00000) | (laddr & 0x003FF000);
|
|
|
|
#if BX_SUPPORT_GLOBAL_PAGES
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE()) { // PGE==1
|
|
combined_access |= pde & TLB_GlobalPage; // {G}
|
|
}
|
|
#endif
|
|
|
|
priv_index =
|
|
#if BX_CPU_LEVEL >= 4
|
|
(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
|
|
#endif
|
|
(pl<<3) | // bit 3
|
|
(combined_access & 0x06) | // bit 2,1
|
|
isWrite; // bit 0
|
|
|
|
if (!priv_check[priv_index]) goto page_fault_access;
|
|
|
|
// Update PDE if A/D bits if needed.
|
|
if (((pde & 0x20)==0) || (isWrite && ((pde&0x40)==0)))
|
|
{
|
|
pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pde_addr, 4, &pde);
|
|
}
|
|
}
|
|
else // Else normal 4Kbyte page...
|
|
#endif
|
|
{
|
|
Bit32u pte;
|
|
|
|
#if (BX_CPU_LEVEL < 6)
|
|
// update PDE if A bit was not set before
|
|
if ( !(pde & 0x20) ) {
|
|
pde |= 0x20;
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pde_addr, 4, &pde);
|
|
}
|
|
#endif
|
|
|
|
// Get page table entry
|
|
bx_phy_address pte_addr = (pde & 0xfffff000) | ((laddr & 0x003ff000) >> 10);
|
|
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pte_addr, 4, &pte);
|
|
|
|
if ( !(pte & 0x01) ) {
|
|
goto page_fault_not_present; // Page Table Entry NOT present
|
|
}
|
|
|
|
// 386 and 486+ have different bahaviour for combining
|
|
// privilege from PDE and PTE.
|
|
#if BX_CPU_LEVEL == 3
|
|
combined_access = (pde | pte) & 0x04; // U/S
|
|
combined_access |= (pde & pte) & 0x02; // R/W
|
|
#else // 486+
|
|
combined_access = (pde & pte) & 0x06; // U/S and R/W
|
|
#if BX_SUPPORT_GLOBAL_PAGES
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE()) {
|
|
combined_access |= (pte & TLB_GlobalPage); // G
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = pte & 0xfffff000;
|
|
|
|
priv_index =
|
|
#if BX_CPU_LEVEL >= 4
|
|
(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
|
|
#endif
|
|
(pl<<3) | // bit 3
|
|
(combined_access & 0x06) | // bit 2,1
|
|
isWrite; // bit 0
|
|
|
|
if (!priv_check[priv_index]) goto page_fault_access;
|
|
|
|
#if (BX_CPU_LEVEL >= 6)
|
|
// update PDE if A bit was not set before
|
|
if ( !(pde & 0x20) ) {
|
|
pde |= 0x20;
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pde_addr, 4, &pde);
|
|
}
|
|
#endif
|
|
|
|
// Update PTE if A/D bits if needed.
|
|
if (((pte & 0x20)==0) || (isWrite && ((pte&0x40)==0)))
|
|
{
|
|
pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, pte_addr, 4, &pte);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Calculate physical memory address and fill in TLB cache entry
|
|
paddress = ppf | poffset;
|
|
#if BX_USE_TLB
|
|
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_TLB_LPF_VALUE(lpf);
|
|
BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
|
|
#endif
|
|
|
|
// b3: Write User OK
|
|
// b2: Write Sys OK
|
|
// b1: Read User OK
|
|
// b0: Read Sys OK
|
|
if ( combined_access & 4 ) { // User
|
|
// User priv; read from {user,sys} OK.
|
|
accessBits = (TLB_ReadUserOK | TLB_ReadSysOK);
|
|
if ( isWrite ) // Current operation is a write (Dirty bit updated)
|
|
{
|
|
if (combined_access & 2) {
|
|
// R/W access from {user,sys} OK.
|
|
accessBits |= (TLB_WriteUserOK | TLB_WriteSysOK);
|
|
}
|
|
else {
|
|
accessBits |= TLB_WriteSysOK; // read only page, only {sys} write allowed
|
|
}
|
|
}
|
|
}
|
|
else { // System
|
|
accessBits = TLB_ReadSysOK; // System priv; read from {sys} OK.
|
|
if ( isWrite ) { // Current operation is a write (Dirty bit updated)
|
|
accessBits |= TLB_WriteSysOK; // write from {sys} OK.
|
|
}
|
|
}
|
|
#if BX_SUPPORT_GLOBAL_PAGES
|
|
accessBits |= combined_access & TLB_GlobalPage; // Global bit
|
|
#endif
|
|
#if BX_USE_TLB
|
|
#if BX_SupportGuest2HostTLB
|
|
// Attempt to get a host pointer to this physical page. Put that
|
|
// pointer in the TLB cache. Note if the request is vetoed, NULL
|
|
// will be returned, and it's OK to OR zero in anyways.
|
|
BX_CPU_THIS_PTR TLB.entry[TLB_index].hostPageAddr =
|
|
(bx_hostpageaddr_t) BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS,
|
|
A20ADDR(ppf), rw, access_type);
|
|
|
|
if (BX_CPU_THIS_PTR TLB.entry[TLB_index].hostPageAddr) {
|
|
// All access allowed also via direct pointer
|
|
accessBits |= (accessBits & 0xf0) >> 4;
|
|
}
|
|
#endif
|
|
BX_CPU_THIS_PTR TLB.entry[TLB_index].accessBits = accessBits;
|
|
#endif
|
|
|
|
return(paddress);
|
|
|
|
// error checking order - page not present, reserved bits, protection
|
|
#define ERROR_NOT_PRESENT 0x00
|
|
#define ERROR_PROTECTION 0x01
|
|
#define ERROR_RESERVED 0x08
|
|
#define ERROR_CODE_ACCESS 0x10
|
|
|
|
#if BX_SUPPORT_X86_64 // keep compiler happy
|
|
page_fault_reserved:
|
|
error_code |= ERROR_RESERVED; // RSVD = 1
|
|
#endif
|
|
|
|
page_fault_access:
|
|
error_code |= ERROR_PROTECTION; // P = 1
|
|
|
|
page_fault_not_present:
|
|
error_code |= (pl << 2) | (isWrite << 1);
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR msr.nxe && (access_type == CODE_ACCESS))
|
|
error_code |= ERROR_CODE_ACCESS; // I/D = 1
|
|
#endif
|
|
BX_CPU_THIS_PTR cr2 = laddr;
|
|
// Invalidate TLB entry.
|
|
#if BX_USE_TLB
|
|
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
|
|
#endif
|
|
#if BX_SUPPORT_X86_64
|
|
BX_DEBUG(("page fault for address %08x%08x @ %08x%08x",
|
|
(Bit32u)(laddr >> 32),(Bit32u)(laddr & 0xffffffff),
|
|
(Bit32u)(RIP >> 32),(Bit32u)(RIP & 0xffffffff)));
|
|
#else
|
|
BX_DEBUG(("page fault for address %08x @ %08x", laddr, EIP));
|
|
#endif
|
|
exception(BX_PF_EXCEPTION, error_code, 0);
|
|
return(0); // keep compiler happy
|
|
}
|
|
|
|
bx_phy_address BX_CPP_AttrRegparmN(3)
|
|
BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
|
|
{
|
|
return translate_linear(laddr, pl, rw, DATA_ACCESS);
|
|
}
|
|
|
|
bx_phy_address BX_CPP_AttrRegparmN(2)
|
|
BX_CPU_C::itranslate_linear(bx_address laddr, unsigned pl)
|
|
{
|
|
return translate_linear(laddr, pl, BX_READ, CODE_ACCESS);
|
|
}
|
|
|
|
#if BX_DEBUGGER || BX_DISASM || BX_INSTRUMENTATION || BX_GDBSTUB
|
|
|
|
bx_bool BX_CPU_C::dbg_xlate_linear2phy(bx_address laddr, bx_phy_address *phy)
|
|
{
|
|
bx_address lpf, poffset, paddress;
|
|
|
|
if (BX_CPU_THIS_PTR cr0.pg == 0) {
|
|
*phy = laddr;
|
|
return 1;
|
|
}
|
|
|
|
lpf = laddr & BX_CONST64(0xfffffffffffff000); // linear page frame
|
|
poffset = laddr & 0x00000fff; // physical offset
|
|
|
|
// see if page is in the TLB first
|
|
#if BX_USE_TLB
|
|
Bit32u TLB_index = BX_TLB_INDEX_OF(lpf);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
|
|
|
|
if (tlbEntry->lpf == BX_TLB_LPF_VALUE(lpf)) {
|
|
paddress = tlbEntry->ppf | poffset;
|
|
*phy = paddress;
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_PAE
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE()) {
|
|
Bit64u pt_address;
|
|
int levels = 3;
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR msr.lme)
|
|
levels = 4;
|
|
#endif
|
|
pt_address = BX_CPU_THIS_PTR cr3_masked;
|
|
Bit64u offset_mask = 0xfff;
|
|
for (int level = levels - 1; level >= 0; --level) {
|
|
Bit64u pte;
|
|
pt_address += 8 * ((laddr >> (12 + 9*level)) & 511);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pt_address, 8, &pte);
|
|
if (!(pte & 1))
|
|
goto page_fault;
|
|
pt_address = pte & BX_CONST64(0x000ffffffffff000);
|
|
if (level == 1 && (pte & 0x80)) { // PSE page
|
|
offset_mask = 0x1fffff;
|
|
break;
|
|
}
|
|
}
|
|
paddress = pt_address + (laddr & offset_mask);
|
|
}
|
|
else // not PAE
|
|
#endif
|
|
{
|
|
Bit32u pt_address = BX_CPU_THIS_PTR cr3_masked;
|
|
Bit32u offset_mask = 0xfff;
|
|
for (int level = 1; level >= 0; --level) {
|
|
Bit32u pte;
|
|
pt_address += 4 * ((laddr >> (12 + 10*level)) & 1023);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, pt_address, 4, &pte);
|
|
if (!(pte & 1))
|
|
goto page_fault;
|
|
pt_address = pte & 0xfffff000;
|
|
if (level == 1 && (pte & 0x80)) { // PSE page
|
|
offset_mask = 0x3fffff;
|
|
break;
|
|
}
|
|
}
|
|
paddress = pt_address + (laddr & offset_mask);
|
|
}
|
|
|
|
*phy = paddress;
|
|
return 1;
|
|
|
|
page_fault:
|
|
*phy = 0;
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void BX_CPP_AttrRegparmN(3)
|
|
BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
|
|
unsigned rw, void *data)
|
|
{
|
|
|
|
#if BX_X86_DEBUGGER
|
|
if (BX_CPU_THIS_PTR dr7 & 0x000000ff) {
|
|
// Only compare debug registers if any breakpoints are enabled
|
|
Bit32u dr6_bits;
|
|
unsigned opa, opb;
|
|
opa = BX_HWDebugMemRW; // Read or Write always compares vs 11b
|
|
if (rw==BX_READ) // only compares vs 11b
|
|
opb = opa;
|
|
else // BX_WRITE or BX_RW; also compare vs 01b
|
|
opb = BX_HWDebugMemW;
|
|
dr6_bits = hwdebug_compare(laddr, length, opa, opb);
|
|
if (dr6_bits) {
|
|
BX_CPU_THIS_PTR debug_trap |= dr6_bits;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
Bit32u pageOffset = laddr & 0x00000fff;
|
|
unsigned xlate_rw = rw;
|
|
if (rw==BX_RW) rw = BX_READ;
|
|
|
|
if (BX_CPU_THIS_PTR cr0.pg) {
|
|
/* check for reference across multiple pages */
|
|
if ( (pageOffset + length) <= 4096 ) {
|
|
// Access within single page.
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 =
|
|
dtranslate_linear(laddr, pl, xlate_rw);
|
|
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
|
|
if (rw == BX_READ) {
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr, BX_CPU_THIS_PTR address_xlation.paddress1, length);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, length, data);
|
|
}
|
|
else {
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr, BX_CPU_THIS_PTR address_xlation.paddress1, length);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, length, data);
|
|
}
|
|
return;
|
|
}
|
|
else {
|
|
// access across 2 pages
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 =
|
|
dtranslate_linear(laddr, pl, xlate_rw);
|
|
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
|
BX_CPU_THIS_PTR address_xlation.len2 = length -
|
|
BX_CPU_THIS_PTR address_xlation.len1;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
|
BX_CPU_THIS_PTR address_xlation.paddress2 =
|
|
dtranslate_linear(laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
pl, xlate_rw);
|
|
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
if (rw == BX_READ) {
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, data);
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
}
|
|
else {
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, data);
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
}
|
|
|
|
#else // BX_BIG_ENDIAN
|
|
if (rw == BX_READ) {
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, data);
|
|
}
|
|
else {
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, data);
|
|
}
|
|
#endif
|
|
return;
|
|
}
|
|
}
|
|
else {
|
|
// Paging off.
|
|
if ( (pageOffset + length) <= 4096 ) {
|
|
// Access within single page.
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 = laddr;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
if (rw == BX_READ) {
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr, laddr, length);
|
|
#if BX_SupportGuest2HostTLB
|
|
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
Bit32u lpf = laddr & 0xfffff000;
|
|
|
|
if (tlbEntry->lpf == BX_TLB_LPF_VALUE(lpf)) {
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, laddr, length, data);
|
|
return;
|
|
}
|
|
// We haven't seen this page, or it's been bumped before.
|
|
|
|
tlbEntry->lpf = BX_TLB_LPF_VALUE(lpf);
|
|
tlbEntry->ppf = lpf;
|
|
// Request a direct write pointer so we can do either R or W.
|
|
tlbEntry->hostPageAddr = (bx_hostpageaddr_t)
|
|
BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS, A20ADDR(lpf), BX_WRITE, DATA_ACCESS);
|
|
|
|
if (! tlbEntry->hostPageAddr) {
|
|
// Direct write vetoed. Try requesting only direct reads.
|
|
tlbEntry->hostPageAddr = (bx_hostpageaddr_t)
|
|
BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS, A20ADDR(lpf), BX_READ, DATA_ACCESS);
|
|
if (tlbEntry->hostPageAddr) {
|
|
// Got direct read pointer OK.
|
|
tlbEntry->accessBits =
|
|
(TLB_ReadSysOK | TLB_ReadUserOK | TLB_ReadSysPtrOK | TLB_ReadUserPtrOK);
|
|
}
|
|
else
|
|
tlbEntry->accessBits = 0;
|
|
}
|
|
else {
|
|
// Got direct write pointer OK. Mark for any operation to succeed.
|
|
tlbEntry->accessBits =(TLB_ReadSysOK | TLB_ReadUserOK | TLB_WriteSysOK | TLB_WriteUserOK |
|
|
TLB_ReadSysPtrOK | TLB_ReadUserPtrOK | TLB_WriteSysPtrOK | TLB_WriteUserPtrOK);
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
// Let access fall through to the following for this iteration.
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, laddr, length, data);
|
|
}
|
|
else { // Write
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr, laddr, length);
|
|
#if BX_SupportGuest2HostTLB
|
|
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
|
|
Bit32u lpf = laddr & 0xfffff000;
|
|
|
|
if (tlbEntry->lpf == BX_TLB_LPF_VALUE(lpf)) {
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, laddr, length, data);
|
|
return;
|
|
}
|
|
// We haven't seen this page, or it's been bumped before.
|
|
|
|
tlbEntry->lpf = BX_TLB_LPF_VALUE(lpf);
|
|
tlbEntry->ppf = lpf;
|
|
// TLB.entry[tlbIndex].ppf field not used for PG==0.
|
|
// Request a direct write pointer so we can do either R or W.
|
|
tlbEntry->hostPageAddr = (bx_hostpageaddr_t)
|
|
BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS, A20ADDR(lpf), BX_WRITE, DATA_ACCESS);
|
|
|
|
if (tlbEntry->hostPageAddr) {
|
|
// Got direct write pointer OK. Mark for any operation to succeed.
|
|
tlbEntry->accessBits = (TLB_ReadSysOK | TLB_ReadUserOK | TLB_WriteSysOK | TLB_WriteUserOK |
|
|
TLB_ReadSysPtrOK | TLB_ReadUserPtrOK | TLB_WriteSysPtrOK | TLB_WriteUserPtrOK);
|
|
}
|
|
else
|
|
tlbEntry->accessBits = 0;
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, laddr, length, data);
|
|
}
|
|
}
|
|
else {
|
|
// Access spans two pages.
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 = laddr;
|
|
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
|
BX_CPU_THIS_PTR address_xlation.len2 = length -
|
|
BX_CPU_THIS_PTR address_xlation.len1;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
|
BX_CPU_THIS_PTR address_xlation.paddress2 = laddr +
|
|
BX_CPU_THIS_PTR address_xlation.len1;
|
|
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
if (rw == BX_READ) {
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, data);
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
}
|
|
else {
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, data);
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
}
|
|
|
|
#else // BX_BIG_ENDIAN
|
|
if (rw == BX_READ) {
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_INSTR_LIN_READ(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, data);
|
|
}
|
|
else {
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_INSTR_LIN_WRITE(BX_CPU_ID, laddr + BX_CPU_THIS_PTR address_xlation.len1,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, data);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
|
|
#else // BX_SUPPORT_PAGING
|
|
|
|
// stub functions for non-support of paging
|
|
|
|
void BX_CPU_C::CR3_change(bx_phy_address value32)
|
|
{
|
|
BX_INFO(("CR3_change(): flush TLB cache"));
|
|
BX_INFO(("Page Directory Base %08x", (unsigned) value32));
|
|
}
|
|
|
|
void BX_CPU_C::access_linear(Bit32u laddr, unsigned length, unsigned pl,
|
|
unsigned rw, void *data)
|
|
{
|
|
/* perhaps put this check before all code which calls this function,
|
|
* so we don't have to here
|
|
*/
|
|
if (BX_CPU_THIS_PTR cr0.pg == 0) {
|
|
if (rw == BX_READ)
|
|
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, laddr, length, data);
|
|
else
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, laddr, length, data);
|
|
return;
|
|
}
|
|
|
|
BX_PANIC(("access_linear: paging not supported"));
|
|
}
|
|
|
|
void BX_CPU_C::INVLPG(bxInstruction_c* i)
|
|
{}
|
|
|
|
#endif // BX_SUPPORT_PAGING
|