249 lines
8.2 KiB
C
249 lines
8.2 KiB
C
/////////////////////////////////////////////////////////////////////////
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// $Id: rombios.h,v 1.16 2010-05-16 14:35:22 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2006 Volker Ruppert
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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/* define it to include QEMU specific code */
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//#define BX_QEMU
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#ifndef LEGACY
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# define BX_ROMBIOS32 1
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#else
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# define BX_ROMBIOS32 0
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#endif
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#define DEBUG_ROMBIOS 0
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#define DEBUG_ATA 0
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#define DEBUG_INT13_HD 0
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#define DEBUG_INT13_CD 0
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#define DEBUG_INT13_ET 0
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#define DEBUG_INT13_FL 0
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#define DEBUG_INT15 0
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#define DEBUG_INT16 0
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#define DEBUG_INT1A 0
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#define DEBUG_INT74 0
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#define DEBUG_APM 0
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#define PANIC_PORT 0x400
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#define PANIC_PORT2 0x401
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#define INFO_PORT 0x402
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#define DEBUG_PORT 0x403
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#define BIOS_PRINTF_HALT 1
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#define BIOS_PRINTF_SCREEN 2
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#define BIOS_PRINTF_INFO 4
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#define BIOS_PRINTF_DEBUG 8
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#define BIOS_PRINTF_ALL (BIOS_PRINTF_SCREEN | BIOS_PRINTF_INFO)
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#define BIOS_PRINTF_DEBHALT (BIOS_PRINTF_SCREEN | BIOS_PRINTF_INFO | BIOS_PRINTF_HALT)
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#define printf(format, p...) bios_printf(BIOS_PRINTF_SCREEN, format, ##p)
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// Defines the output macros.
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// BX_DEBUG goes to INFO port until we can easily choose debug info on a
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// per-device basis. Debug info are sent only in debug mode
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#if DEBUG_ROMBIOS
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# define BX_DEBUG(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p)
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#else
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# define BX_DEBUG(format, p...)
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#endif
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#define BX_INFO(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p)
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#define BX_PANIC(format, p...) bios_printf(BIOS_PRINTF_DEBHALT, format, ##p)
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/* put the MP float table and ACPI RSDP in EBDA and the MP and ACPI tables in
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high memory. Linux kernels < 2.6.30 might not work with this configuration */
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//#define BX_USE_EBDA_TABLES
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#define ACPI_DATA_SIZE 0x00010000L
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#define MPTABLE_MAX_SIZE 0x00002000
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#define PM_IO_BASE 0xb000
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#define SMB_IO_BASE 0xb100
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#define SMP_MSR_ADDR 0x0510
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// Define the application NAME
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#if defined(BX_QEMU)
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# define BX_APPNAME "QEMU"
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# define BX_APPVENDOR "QEMU"
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#else
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# define BX_APPNAME "Bochs"
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# define BX_APPVENDOR "The Bochs Project"
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#endif
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#define E820_RAM 1
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#define E820_RESERVED 2
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#define E820_ACPI 3
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#define E820_NVS 4
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#define E820_UNUSABLE 5
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#define BX_CPU 3
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#define BX_USE_PS2_MOUSE 1
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#define BX_CALL_INT15_4F 1
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#define BX_USE_EBDA 1
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#define BX_SUPPORT_FLOPPY 1
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#define BX_FLOPPY_ON_CNT 37 /* 2 seconds */
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#define BX_PCIBIOS 1
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#define BX_APM 1
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#define BX_PNPBIOS 1
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/* define it if the (emulated) hardware supports SMM mode */
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#define BX_USE_SMM
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#define BX_USE_ATADRV 1
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#define BX_ELTORITO_BOOT 1
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#define BX_MAX_ATA_INTERFACES 4
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#define BX_MAX_ATA_DEVICES (BX_MAX_ATA_INTERFACES*2)
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#define BX_VIRTUAL_PORTS 1 /* normal output to Bochs ports */
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#define BX_DEBUG_SERIAL 0 /* output to COM1 */
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/* model byte 0xFC = AT */
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#define SYS_MODEL_ID 0xFC
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#define SYS_SUBMODEL_ID 0x00
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#define BIOS_REVISION 1
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#define BIOS_CONFIG_TABLE 0xe6f5
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#ifndef BIOS_BUILD_DATE
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# define BIOS_BUILD_DATE "06/23/99"
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#endif
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// 1K of base memory used for Extended Bios Data Area (EBDA)
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// EBDA is used for PS/2 mouse support, and IDE BIOS, etc.
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#define EBDA_SEG 0x9FC0
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#define EBDA_SIZE 1 // In KiB
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#define BASE_MEM_IN_K (640 - EBDA_SIZE)
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/* IPL_SIZE bytes at 0x9ff00 are used for the IPL boot table. */
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#define IPL_SEG 0x9ff0
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#define IPL_TABLE_OFFSET 0x0000
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#define IPL_TABLE_ENTRIES 8
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#define IPL_COUNT_OFFSET 0x0080 /* u16: number of valid table entries */
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#define IPL_SEQUENCE_OFFSET 0x0082 /* u16: next boot device */
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#define IPL_BOOTFIRST_OFFSET 0x0084 /* u16: user selected device */
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#define IPL_SIZE 0x86
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#define IPL_TYPE_FLOPPY 0x01
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#define IPL_TYPE_HARDDISK 0x02
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#define IPL_TYPE_CDROM 0x03
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#define IPL_TYPE_BEV 0x80
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/* Ports */
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#define PORT_DMA_ADDR_2 0x0004
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#define PORT_DMA_CNT_2 0x0005
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#define PORT_DMA1_MASK_REG 0x000a
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#define PORT_DMA1_MODE_REG 0x000b
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#define PORT_DMA1_CLEAR_FF_REG 0x000c
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#define PORT_DMA1_MASTER_CLEAR 0x000d
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#define PORT_PIC1_CMD 0x0020
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#define PORT_PIC1_DATA 0x0021
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#define PORT_PIT_COUNTER0 0x0040
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#define PORT_PIT_MODE 0x0043
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#define PORT_PS2_DATA 0x0060
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#define PORT_PS2_CTRLB 0x0061
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#define PORT_PS2_STATUS 0x0064
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#define PORT_CMOS_INDEX 0x0070
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#define PORT_CMOS_DATA 0x0071
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#define PORT_DIAG 0x0080
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#define PORT_DMA_PAGE_2 0x0081
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#define PORT_A20 0x0092
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#define PORT_PIC2_CMD 0x00a0
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#define PORT_PIC2_DATA 0x00a1
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#define PORT_DMA2_MASK_REG 0x00d4
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#define PORT_DMA2_MODE_REG 0x00d6
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#define PORT_DMA2_MASTER_CLEAR 0x00da
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#define PORT_ATA2_CMD_BASE 0x0170
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#define PORT_ATA1_CMD_BASE 0x01f0
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#define PORT_FD_DOR 0x03f2
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#define PORT_FD_STATUS 0x03f4
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#define PORT_FD_DATA 0x03f5
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#define CPUID_MSR (1 << 5)
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#define CPUID_APIC (1 << 9)
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#define CPUID_MTRR (1 << 12)
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#define APIC_BASE ((uint8_t *)0xfee00000)
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#define APIC_ICR_LOW 0x300
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#define APIC_SVR 0x0F0
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#define APIC_ID 0x020
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#define APIC_LVT3 0x370
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#define APIC_ENABLED 0x0100
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#define AP_BOOT_ADDR 0x9f000
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#define SMI_CMD_IO_ADDR 0xb2
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#define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
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#define MSR_MTRRcap 0x000000fe
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#define MSR_MTRRfix64K_00000 0x00000250
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#define MSR_MTRRfix16K_80000 0x00000258
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#define MSR_MTRRfix16K_A0000 0x00000259
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#define MSR_MTRRfix4K_C0000 0x00000268
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#define MSR_MTRRfix4K_C8000 0x00000269
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#define MSR_MTRRfix4K_D0000 0x0000026a
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#define MSR_MTRRfix4K_D8000 0x0000026b
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#define MSR_MTRRfix4K_E0000 0x0000026c
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#define MSR_MTRRfix4K_E8000 0x0000026d
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#define MSR_MTRRfix4K_F0000 0x0000026e
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#define MSR_MTRRfix4K_F8000 0x0000026f
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#define MSR_MTRRdefType 0x000002ff
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define MTRR_MEMTYPE_UC 0
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#define MTRR_MEMTYPE_WC 1
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#define MTRR_MEMTYPE_WT 4
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#define MTRR_MEMTYPE_WP 5
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#define MTRR_MEMTYPE_WB 6
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#define QEMU_CFG_CTL_PORT 0x510
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#define QEMU_CFG_DATA_PORT 0x511
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#define QEMU_CFG_SIGNATURE 0x00
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#define QEMU_CFG_ID 0x01
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#define QEMU_CFG_UUID 0x02
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#define PCI_ADDRESS_SPACE_MEM 0x00
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#define PCI_ADDRESS_SPACE_IO 0x01
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#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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#define PCI_DEVICES_MAX 64
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_82441 0x1237
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#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
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#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
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#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
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#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
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#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
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#define PCI_VENDOR_ID_IBM 0x1014
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#define PCI_VENDOR_ID_APPLE 0x106b
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