5cc04b9955
XOP: few instructions are still missing, coming soon
BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
380 lines
8.6 KiB
C++
380 lines
8.6 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64
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static unsigned partial_add(Bit32u *sum, Bit32u b)
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{
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Bit32u t = *sum;
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*sum += b;
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return (*sum < t);
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}
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void long_mul(Bit128u *product, Bit64u op1, Bit64u op2)
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{
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Bit32u op_1[2],op_2[2];
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Bit32u result[5];
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Bit64u nn;
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unsigned c;
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int i,j,k;
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op_1[0] = (Bit32u)(op1 & 0xffffffff);
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op_1[1] = (Bit32u)(op1 >> 32);
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op_2[0] = (Bit32u)(op2 & 0xffffffff);
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op_2[1] = (Bit32u)(op2 >> 32);
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for (i = 0; i < 4; i++) result[i] = 0;
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for (i = 0; i < 2; i++) {
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for (j = 0; j < 2; j++) {
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nn = (Bit64u) op_1[i] * (Bit64u) op_2[j];
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k = i + j;
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c = partial_add(&result[k++], (Bit32u)(nn & 0xffffffff));
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c = partial_add(&result[k++], (Bit32u)(nn >> 32) + c);
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while (k < 4 && c != 0) {
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c = partial_add(&result[k++], c);
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}
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}
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}
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product->lo = result[0] + ((Bit64u) result[1] << 32);
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product->hi = result[2] + ((Bit64u) result[3] << 32);
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}
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void long_neg(Bit128s *n)
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{
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Bit64u t = n->lo;
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n->lo = - (Bit64s)(n->lo);
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if (t - 1 > t) --n->hi;
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n->hi = ~n->hi;
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}
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void long_imul(Bit128s *product, Bit64s op1, Bit64s op2)
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{
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unsigned s1,s2;
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if ((s1 = (op1 < 0))) op1 = -op1;
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if ((s2 = (op2 < 0))) op2 = -op2;
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long_mul((Bit128u*)product,(Bit64u)op1,(Bit64u)op2);
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if (s1 ^ s2)
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long_neg(product);
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}
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void long_shl(Bit128u *a)
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{
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Bit64u c = a->lo >> 63;
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a->lo <<= 1;
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a->hi <<= 1;
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a->hi |= c;
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}
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void long_shr(Bit128u *a)
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{
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Bit64u c;
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c = a->hi << 63;
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a->hi >>= 1;
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a->lo >>= 1;
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a->lo |= c;
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}
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unsigned long_sub(Bit128u *a,Bit128u *b)
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{
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Bit64u t = a->lo;
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a->lo -= b->lo;
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int c = (a->lo > t);
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t = a -> hi;
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a->hi -= b->hi + c;
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return(a->hi > t);
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}
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int long_le(Bit128u *a,Bit128u *b)
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{
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if (a->hi == b->hi) {
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return(a->lo <= b->lo);
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} else {
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return(a->hi <= b->hi);
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}
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}
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void long_div(Bit128u *quotient,Bit64u *remainder,const Bit128u *dividend,Bit64u divisor)
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{
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/*
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n := 0;
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while (divisor <= dividend) do
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inc(n);
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divisor := divisor * 2;
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end;
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quotient := 0;
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while n > 0 do
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divisor := divisor div 2;
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quotient := quotient * 2;
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temp := dividend;
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dividend := dividend - divisor;
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if temp > dividend then
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dividend := temp;
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else
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inc(quotient);
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end;
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dec(n);
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end;
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remainder := dividend;
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*/
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Bit128u d,acc,q,temp;
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int n,c;
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d.lo = divisor;
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d.hi = 0;
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acc.lo = dividend->lo;
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acc.hi = dividend->hi;
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q.lo = 0;
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q.hi = 0;
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n = 0;
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while (long_le(&d,&acc) && n < 128) {
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long_shl(&d);
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n++;
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}
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while (n > 0) {
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long_shr(&d);
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long_shl(&q);
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temp.lo = acc.lo;
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temp.hi = acc.hi;
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c = long_sub(&acc,&d);
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if (c) {
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acc.lo = temp.lo;
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acc.hi = temp.hi;
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} else {
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q.lo++;
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}
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n--;
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}
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*remainder = acc.lo;
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quotient->lo = q.lo;
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quotient->hi = q.hi;
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}
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void long_idiv(Bit128s *quotient,Bit64s *remainder,Bit128s *dividend,Bit64s divisor)
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{
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unsigned s1,s2;
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Bit128s temp;
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temp = *dividend;
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if ((s1 = (temp.hi < 0))) {
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long_neg(&temp);
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}
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if ((s2 = (divisor < 0))) divisor = -divisor;
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long_div((Bit128u*)quotient,(Bit64u*)remainder,(Bit128u*)&temp,divisor);
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if (s1 ^ s2) {
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long_neg(quotient);
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}
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if (s1) {
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*remainder = -*remainder;
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}
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_RAXEqR(bxInstruction_c *i)
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{
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Bit128u product_128;
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Bit64u op1_64 = RAX;
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Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
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// product_128 = ((Bit128u) op1_64) * ((Bit128u) op2_64);
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// product_64l = (Bit64u) (product_128 & 0xFFFFFFFFFFFFFFFF);
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// product_64h = (Bit64u) (product_128 >> 64);
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long_mul(&product_128,op1_64,op2_64);
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/* now write product back to destination */
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RAX = product_128.lo;
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RDX = product_128.hi;
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/* set EFLAGS */
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SET_FLAGS_OSZAPC_LOGIC_64(product_128.lo);
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if(product_128.hi != 0)
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{
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_RAXEqR(bxInstruction_c *i)
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{
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Bit128s product_128;
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Bit64s op1_64 = RAX;
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Bit64s op2_64 = BX_READ_64BIT_REG(i->rm());
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// product_128 = ((Bit128s) op1_64) * ((Bit128s) op2_64);
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// product_64l = (Bit64u) (product_128 & 0xFFFFFFFFFFFFFFFF);
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// product_64h = (Bit64u) (product_128 >> 64);
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long_imul(&product_128,op1_64,op2_64);
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/* now write product back to destination */
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RAX = product_128.lo;
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RDX = product_128.hi;
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/* set eflags:
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* IMUL r/m64: condition for clearing CF & OF:
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* RDX:RAX = sign-extend of RAX
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*/
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SET_FLAGS_OSZAPC_LOGIC_64(product_128.lo);
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/* magic compare between RDX:RAX and sign extended RAX */
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if (((Bit64u)(product_128.hi) + (product_128.lo >> 63)) != 0) {
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_RAXEqR(bxInstruction_c *i)
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{
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Bit64u remainder_64, quotient_64l;
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Bit128u op1_128, quotient_128;
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Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
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if (op2_64 == 0) {
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exception(BX_DE_EXCEPTION, 0);
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}
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op1_128.lo = RAX;
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op1_128.hi = RDX;
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// quotient_128 = op1_128 / op2_64;
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// remainder_64 = (Bit64u) (op1_128 % op2_64);
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// quotient_64l = (Bit64u) (quotient_128 & 0xFFFFFFFFFFFFFFFF);
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long_div("ient_128,&remainder_64,&op1_128,op2_64);
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quotient_64l = quotient_128.lo;
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if (quotient_128.hi != 0)
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exception(BX_DE_EXCEPTION, 0);
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/* set EFLAGS:
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* DIV affects the following flags: O,S,Z,A,P,C are undefined
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*/
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/* now write quotient back to destination */
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RAX = quotient_64l;
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RDX = remainder_64;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_RAXEqR(bxInstruction_c *i)
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{
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Bit64s remainder_64, quotient_64l;
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Bit128s op1_128, quotient_128;
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op1_128.lo = RAX;
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op1_128.hi = RDX;
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/* check MIN_INT case */
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if ((op1_128.hi == (Bit64s) BX_CONST64(0x8000000000000000)) && (!op1_128.lo))
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exception(BX_DE_EXCEPTION, 0);
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Bit64s op2_64 = BX_READ_64BIT_REG(i->rm());
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if (op2_64 == 0) {
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exception(BX_DE_EXCEPTION, 0);
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}
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// quotient_128 = op1_128 / op2_64;
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// remainder_64 = (Bit64s) (op1_128 % op2_64);
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// quotient_64l = (Bit64s) (quotient_128 & 0xFFFFFFFFFFFFFFFF);
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long_idiv("ient_128,&remainder_64,&op1_128,op2_64);
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quotient_64l = quotient_128.lo;
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if ((!(quotient_128.lo & BX_CONST64(0x8000000000000000)) && quotient_128.hi != (Bit64s) 0) ||
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((quotient_128.lo & BX_CONST64(0x8000000000000000)) && quotient_128.hi != (Bit64s) BX_CONST64(0xffffffffffffffff)))
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{
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exception(BX_DE_EXCEPTION, 0);
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}
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/* set EFLAGS:
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* IDIV affects the following flags: O,S,Z,A,P,C are undefined
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*/
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/* now write quotient back to destination */
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RAX = quotient_64l;
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RDX = remainder_64;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GqEqIdR(bxInstruction_c *i)
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{
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Bit128s product_128;
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Bit64s op1_64 = BX_READ_64BIT_REG(i->rm());
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Bit64s op2_64 = (Bit32s) i->Id();
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long_imul(&product_128,op1_64,op2_64);
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/* now write product back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), product_128.lo);
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SET_FLAGS_OSZAPC_LOGIC_64(product_128.lo);
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if (((Bit64u)(product_128.hi) + (product_128.lo >> 63)) != 0) {
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GqEqR(bxInstruction_c *i)
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{
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Bit128s product_128;
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Bit64s op1_64 = BX_READ_64BIT_REG(i->nnn());
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Bit64s op2_64 = BX_READ_64BIT_REG(i->rm());
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long_imul(&product_128,op1_64,op2_64);
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/* now write product back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), product_128.lo);
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SET_FLAGS_OSZAPC_LOGIC_64(product_128.lo);
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if (((Bit64u)(product_128.hi) + (product_128.lo >> 63)) != 0) {
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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#endif /* if BX_SUPPORT_X86_64 */
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