bdb89cd364
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
864 lines
19 KiB
C++
864 lines
19 KiB
C++
// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::INC_ERX(BxInstruction_t *i)
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{
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Bit32u erx;
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erx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
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SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_INC32);
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}
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void
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BX_CPU_C::DEC_ERX(BxInstruction_t *i)
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{
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Bit32u erx;
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erx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
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SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_DEC32);
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}
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void
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BX_CPU_C::ADD_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, sum_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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sum_32 = op1_32 + op2_32;
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/* now write sum back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, sum_32);
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}
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else {
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write_RMW_virtual_dword(sum_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
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}
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void
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BX_CPU_C::ADD_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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sum_32 = op1_32 + op2_32;
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/* now write sum back to destination */
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BX_WRITE_32BIT_REG(i->nnn, sum_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
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}
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void
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BX_CPU_C::ADD_EAXId(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 + op2_32;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
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}
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void
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BX_CPU_C::ADC_EdGd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, sum_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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sum_32 = op1_32 + op2_32 + temp_CF;
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/* now write sum back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, sum_32);
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}
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else {
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write_RMW_virtual_dword(sum_32);
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}
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
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temp_CF);
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}
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void
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BX_CPU_C::ADC_GdEd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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sum_32 = op1_32 + op2_32 + temp_CF;
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/* now write sum back to destination */
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BX_WRITE_32BIT_REG(i->nnn, sum_32);
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
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temp_CF);
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}
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void
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BX_CPU_C::ADC_EAXId(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 + op2_32 + temp_CF;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_EdGd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, diff_32);
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}
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else {
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write_RMW_virtual_dword(diff_32);
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}
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_GdEd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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BX_WRITE_32BIT_REG(i->nnn, diff_32);
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_EAXId(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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EAX = diff_32;
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_EdId(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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op2_32 = i->Id;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, diff_32);
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}
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else {
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write_RMW_virtual_dword(diff_32);
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}
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SUB_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - op2_32;
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/* now write diff back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, diff_32);
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}
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else {
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write_RMW_virtual_dword(diff_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
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}
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void
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BX_CPU_C::SUB_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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diff_32 = op1_32 - op2_32;
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/* now write diff back to destination */
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BX_WRITE_32BIT_REG(i->nnn, diff_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
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}
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void
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BX_CPU_C::SUB_EAXId(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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diff_32 = op1_32 - op2_32;
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/* now write diff back to destination */
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EAX = diff_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
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}
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void
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BX_CPU_C::CMP_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
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}
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void
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BX_CPU_C::CMP_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
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}
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void
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BX_CPU_C::CMP_EAXId(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
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}
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void
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BX_CPU_C::CWDE(BxInstruction_t *i)
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{
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/* CBW: no flags are effected */
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EAX = (Bit16s) AX;
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}
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void
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BX_CPU_C::CDQ(BxInstruction_t *i)
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{
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/* CWD: no flags are affected */
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if (EAX & 0x80000000) {
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EDX = 0xFFFFFFFF;
|
|
}
|
|
else {
|
|
EDX = 0x00000000;
|
|
}
|
|
}
|
|
|
|
// Some info on the opcodes at {0F,A6} and {0F,A7}
|
|
// On 386 steps A0-B0:
|
|
// {OF,A6} = XBTS
|
|
// {OF,A7} = IBTS
|
|
// On 486 steps A0-B0:
|
|
// {OF,A6} = CMPXCHG 8
|
|
// {OF,A7} = CMPXCHG 16|32
|
|
//
|
|
// On 486 >= B steps, and further processors, the
|
|
// CMPXCHG instructions were moved to opcodes:
|
|
// {OF,B0} = CMPXCHG 8
|
|
// {OF,B1} = CMPXCHG 16|32
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG_XBTS(BxInstruction_t *i)
|
|
{
|
|
BX_INFO(("CMPXCHG_XBTS:\n"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG_IBTS(BxInstruction_t *i)
|
|
{
|
|
BX_INFO(("CMPXCHG_IBTS:\n"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::XADD_EdGd(BxInstruction_t *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u op2_32, op1_32, sum_32;
|
|
|
|
/* XADD dst(r/m), src(r)
|
|
* temp <-- src + dst | sum = op2 + op1
|
|
* src <-- dst | op2 = op1
|
|
* dst <-- tmp | op1 = sum
|
|
*/
|
|
|
|
/* op2 is a register, i->rm_addr is an index of a register */
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn);
|
|
|
|
/* op1 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
sum_32 = op1_32 + op2_32;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
// and write destination into source
|
|
// Note: if both op1 & op2 are registers, the last one written
|
|
// should be the sum, as op1 & op2 may be the same register.
|
|
// For example: XADD AL, AL
|
|
BX_WRITE_32BIT_REG(i->nnn, op1_32);
|
|
BX_WRITE_32BIT_REG(i->rm, sum_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(sum_32);
|
|
/* and write destination into source */
|
|
BX_WRITE_32BIT_REG(i->nnn, op1_32);
|
|
}
|
|
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XADD32);
|
|
#else
|
|
BX_PANIC(("XADD_EdGd: not supported on < 80486\n"));
|
|
#endif
|
|
}
|
|
|
|
|
|
|
|
void
|
|
BX_CPU_C::ADD_EdId(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, sum_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
sum_32 = op1_32 + op2_32;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, sum_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(sum_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::ADC_EdId(BxInstruction_t *i)
|
|
{
|
|
Boolean temp_CF;
|
|
|
|
temp_CF = get_CF();
|
|
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, sum_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
sum_32 = op1_32 + op2_32 + temp_CF;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, sum_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(sum_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
|
|
temp_CF);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::SUB_EdId(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, diff_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = op1_32 - op2_32;
|
|
|
|
/* now write diff back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, diff_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(diff_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::CMP_EdId(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, diff_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = op1_32 - op2_32;
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
BX_CPU_C::NEG_Ed(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op1_32, diff_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = 0 - op1_32;
|
|
|
|
/* now write diff back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, diff_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(diff_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, 0, diff_32, BX_INSTR_NEG32);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::INC_Ed(BxInstruction_t *i)
|
|
{
|
|
Bit32u op1_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
op1_32++;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, op1_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(op1_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAP_32(0, 0, op1_32, BX_INSTR_INC32);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::DEC_Ed(BxInstruction_t *i)
|
|
{
|
|
Bit32u op1_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
op1_32--;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, op1_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(op1_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAP_32(0, 0, op1_32, BX_INSTR_DEC32);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG_EdGd(BxInstruction_t *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u op2_32, op1_32, diff_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = EAX - op1_32;
|
|
|
|
SET_FLAGS_OSZAPC_32(EAX, op1_32, diff_32, BX_INSTR_CMP32);
|
|
|
|
if (diff_32 == 0) { // if accumulator == dest
|
|
// ZF = 1
|
|
set_ZF(1);
|
|
// dest <-- src
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn);
|
|
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, op2_32);
|
|
}
|
|
else {
|
|
write_RMW_virtual_dword(op2_32);
|
|
}
|
|
}
|
|
else {
|
|
// ZF = 0
|
|
set_ZF(0);
|
|
// accumulator <-- dest
|
|
EAX = op1_32;
|
|
}
|
|
#else
|
|
BX_PANIC(("CMPXCHG_EdGd:\n"));
|
|
#endif
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG8B(BxInstruction_t *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 5) || (BX_CPU_LEVEL_HACKED >= 5)
|
|
if (i->mod != 0xc0) {
|
|
BX_INFO(("CMPXCHG8B: dest is reg: #UD\n"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
BX_PANIC(("CMPXCHG8B: not implemented yet\n"));
|
|
#else
|
|
BX_INFO(("CMPXCHG8B: not implemented yet\n"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|