722 lines
24 KiB
C++
722 lines
24 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: pic.cc,v 1.15 2001-11-19 14:41:03 bdenney Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#define LOG_THIS bx_pic.
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bx_pic_c bx_pic;
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#if BX_USE_PIC_SMF
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#define this (&bx_pic)
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#endif
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bx_pic_c::bx_pic_c(void)
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{
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put("PIC");
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settype(PICLOG);
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}
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bx_pic_c::~bx_pic_c(void)
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{
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// nothing for now
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}
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void
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bx_pic_c::init(bx_devices_c *d)
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{
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BX_PIC_THIS devices = d;
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/* 8259 PIC (Programmable Interrupt Controller) */
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BX_PIC_THIS devices->register_io_read_handler(this, read_handler, 0x0020, "8259 PIC");
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BX_PIC_THIS devices->register_io_read_handler(this, read_handler, 0x0021, "8259 PIC");
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BX_PIC_THIS devices->register_io_read_handler(this, read_handler, 0x00A0, "8259 PIC");
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BX_PIC_THIS devices->register_io_read_handler(this, read_handler, 0x00A1, "8259 PIC");
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BX_PIC_THIS devices->register_io_write_handler(this, write_handler, 0x0020, "8259 PIC");
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BX_PIC_THIS devices->register_io_write_handler(this, write_handler, 0x0021, "8259 PIC");
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BX_PIC_THIS devices->register_io_write_handler(this, write_handler, 0x00A0, "8259 PIC");
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BX_PIC_THIS devices->register_io_write_handler(this, write_handler, 0x00A1, "8259 PIC");
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BX_PIC_THIS s.master_pic.single_PIC = 0;
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BX_PIC_THIS s.master_pic.interrupt_offset = 0x08; /* IRQ0 = INT 0x08 */
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/* slave PIC connected to IRQ2 of master */
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BX_PIC_THIS s.master_pic.u.slave_connect_mask = 0x04;
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BX_PIC_THIS s.master_pic.sfnm = 0; /* normal nested mode */
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BX_PIC_THIS s.master_pic.buffered_mode = 0; /* unbuffered mode */
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BX_PIC_THIS s.master_pic.master_slave = 0; /* no meaning, buffered_mode=0 */
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BX_PIC_THIS s.master_pic.auto_eoi = 0; /* manual EOI from CPU */
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BX_PIC_THIS s.master_pic.imr = 0xFF; /* all IRQ's initially masked */
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BX_PIC_THIS s.master_pic.isr = 0x00; /* no IRQ's in service */
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BX_PIC_THIS s.master_pic.irr = 0x00; /* no IRQ's requested */
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BX_PIC_THIS s.master_pic.read_reg_select = 0; /* IRR */
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BX_PIC_THIS s.master_pic.irq = 0;
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BX_PIC_THIS s.master_pic.INT = 0;
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BX_PIC_THIS s.master_pic.init.in_init = 0;
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BX_PIC_THIS s.master_pic.init.requires_4 = 0;
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BX_PIC_THIS s.master_pic.init.byte_expected = 0;
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BX_PIC_THIS s.master_pic.special_mask = 0;
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BX_PIC_THIS s.slave_pic.single_PIC = 0;
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BX_PIC_THIS s.slave_pic.interrupt_offset = 0x70; /* IRQ8 = INT 0x70 */
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BX_PIC_THIS s.slave_pic.u.slave_id = 0x02; /* slave PIC connected to IRQ2 of master */
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BX_PIC_THIS s.slave_pic.sfnm = 0; /* normal nested mode */
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BX_PIC_THIS s.slave_pic.buffered_mode = 0; /* unbuffered mode */
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BX_PIC_THIS s.slave_pic.master_slave = 0; /* no meaning, buffered_mode=0 */
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BX_PIC_THIS s.slave_pic.auto_eoi = 0; /* manual EOI from CPU */
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BX_PIC_THIS s.slave_pic.imr = 0xFF; /* all IRQ's initially masked */
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BX_PIC_THIS s.slave_pic.isr = 0x00; /* no IRQ's in service */
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BX_PIC_THIS s.slave_pic.irr = 0x00; /* no IRQ's requested */
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BX_PIC_THIS s.slave_pic.read_reg_select = 0; /* IRR */
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BX_PIC_THIS s.slave_pic.irq = 0;
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BX_PIC_THIS s.slave_pic.INT = 0;
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BX_PIC_THIS s.slave_pic.init.in_init = 0;
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BX_PIC_THIS s.slave_pic.init.requires_4 = 0;
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BX_PIC_THIS s.slave_pic.init.byte_expected = 0;
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BX_PIC_THIS s.slave_pic.special_mask = 0;
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u
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bx_pic_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_PIC_SMF
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bx_pic_c *class_ptr = (bx_pic_c *) this_ptr;
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return( class_ptr->read(address, io_len) );
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}
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Bit32u
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bx_pic_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PIC_SMF
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if (io_len > 1)
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BX_PANIC(("io read from port %04x, len=%u", (unsigned) address,
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(unsigned) io_len));
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BX_DEBUG(("IO read from %04x", (unsigned) address));
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/*
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8259A PIC
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*/
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switch (address) {
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case 0x20:
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if (BX_PIC_THIS s.master_pic.read_reg_select) { /* ISR */
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if (bx_dbg.pic) BX_INFO(("read master ISR = %02x",
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(unsigned) BX_PIC_THIS s.master_pic.isr));
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return(BX_PIC_THIS s.master_pic.isr);
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}
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else { /* IRR */
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if (bx_dbg.pic) BX_INFO(("read master IRR = %02x",
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(unsigned) BX_PIC_THIS s.master_pic.irr));
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return(BX_PIC_THIS s.master_pic.irr);
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}
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break;
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case 0x21:
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if (bx_dbg.pic) BX_INFO(("read master IMR = %02x",
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(unsigned) BX_PIC_THIS s.master_pic.imr));
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return(BX_PIC_THIS s.master_pic.imr);
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break;
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case 0xA0:
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if (BX_PIC_THIS s.slave_pic.read_reg_select) { /* ISR */
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if (bx_dbg.pic) BX_INFO(("read slave ISR = %02x",
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(unsigned) BX_PIC_THIS s.slave_pic.isr));
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return(BX_PIC_THIS s.slave_pic.isr);
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}
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else { /* IRR */
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if (bx_dbg.pic) BX_INFO(("read slave IRR = %02x",
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(unsigned) BX_PIC_THIS s.slave_pic.irr));
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return(BX_PIC_THIS s.slave_pic.irr);
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}
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break;
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case 0xA1:
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if (bx_dbg.pic) BX_INFO(("read slave IMR = %02x",
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(unsigned) BX_PIC_THIS s.slave_pic.imr));
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return(BX_PIC_THIS s.slave_pic.imr);
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break;
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}
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BX_PANIC(("io read to address %04x", (unsigned) address));
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return(0); /* default if not found above */
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void
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bx_pic_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PIC_SMF
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bx_pic_c *class_ptr = (bx_pic_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void
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bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PIC_SMF
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int irq;
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if (io_len > 1)
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BX_PANIC(("io write to port %04x, len=%u", (unsigned) address,
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(unsigned) io_len));
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if (bx_dbg.pic)
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BX_INFO(("IO write to %04x = %02x",
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(unsigned) address, (unsigned) value));
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/*
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8259A PIC
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*/
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switch (address) {
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case 0x20:
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if (value & 0x10) { /* initialization command 1 */
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// (mch) Ignore...
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// BX_INFO(("pic:master: init command 1 found %02x", (unsigned) value));
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if (bx_dbg.pic) {
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BX_INFO(("pic:master: init command 1 found"));
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BX_INFO((" requires 4 = %u",
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(unsigned) (value & 0x01) ));
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BX_INFO((" cascade mode: [0=cascade,1=single] %u",
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(unsigned) ((value & 0x02) >> 1)));
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}
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BX_PIC_THIS s.master_pic.init.in_init = 1;
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BX_PIC_THIS s.master_pic.init.requires_4 = (value & 0x01);
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BX_PIC_THIS s.master_pic.init.byte_expected = 2; /* operation command 2 */
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BX_PIC_THIS s.master_pic.imr = 0xFF; /* all IRQ's initially masked */
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BX_PIC_THIS s.master_pic.isr = 0x00; /* no IRQ's in service */
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BX_PIC_THIS s.master_pic.irr = 0x00; /* no IRQ's requested */
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BX_PIC_THIS s.master_pic.INT = 0; /* reprogramming clears previous INTR request */
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if ( (value & 0x02) == 1 )
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BX_PANIC(("pic:master: init command: single mode"));
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BX_SET_INTR(0);
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return;
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}
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if ( (value & 0x18) == 0x08 ) { /* OCW3 */
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Bit8u special_mask, poll, read_op;
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special_mask = (value & 0x60) >> 5;
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poll = (value & 0x04) >> 2;
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read_op = (value & 0x03);
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if (poll)
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BX_PANIC(("pic:master:OCW3: poll bit set"));
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if (read_op == 0x02) /* read IRR */
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BX_PIC_THIS s.master_pic.read_reg_select = 0;
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else if (read_op == 0x03) /* read ISR */
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BX_PIC_THIS s.master_pic.read_reg_select = 1;
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if (special_mask == 0x02) { /* cancel special mask */
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BX_PIC_THIS s.master_pic.special_mask = 0;
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}
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else if (special_mask == 0x03) { /* set specific mask */
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BX_PIC_THIS s.master_pic.special_mask = 1;
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service_master_pic();
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}
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return;
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}
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/* OCW2 */
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switch (value) {
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case 0x00: // Rotate in Auto-EOI mode
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BX_PANIC(("PIC: Rotate in Auto-EOI mode command received."));
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case 0x0A: /* select read interrupt request register */
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BX_PIC_THIS s.master_pic.read_reg_select = 0;
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break;
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case 0x0B: /* select read interrupt in-service register */
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BX_PIC_THIS s.master_pic.read_reg_select = 1;
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break;
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case 0x20: /* end of interrupt command */
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/* clear highest current in service bit */
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for (irq=0; irq<=7; irq++) {
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if (BX_PIC_THIS s.master_pic.isr & (1 << irq)) {
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BX_PIC_THIS s.master_pic.isr &= ~(1 << irq);
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break; /* out of for loop */
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}
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}
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service_master_pic();
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break;
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case 0x60: /* specific EOI 0 */
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case 0x61: /* specific EOI 1 */
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case 0x62: /* specific EOI 2 */
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case 0x63: /* specific EOI 3 */
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case 0x64: /* specific EOI 4 */
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case 0x65: /* specific EOI 5 */
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case 0x66: /* specific EOI 6 */
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case 0x67: /* specific EOI 7 */
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BX_PIC_THIS s.master_pic.isr &= ~(1 << (value-0x60));
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BX_PIC_THIS s.master_pic.irr &= ~(1 << (value-0x60));
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service_master_pic();
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break;
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// IRQ lowest priority commands
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case 0xC0: // 0 7 6 5 4 3 2 1
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case 0xC1: // 1 0 7 6 5 4 3 2
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case 0xC2: // 2 1 0 7 6 5 4 3
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case 0xC3: // 3 2 1 0 7 6 5 4
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case 0xC4: // 4 3 2 1 0 7 6 5
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case 0xC5: // 5 4 3 2 1 0 7 6
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case 0xC6: // 6 5 4 3 2 1 0 7
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case 0xC7: // 7 6 5 4 3 2 1 0
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// ignore for now
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BX_INFO(("IRQ lowest command 0x%x", value));
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break;
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default:
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BX_PANIC(("PIC: write to port 20h = %02x", value));
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} /* switch (value) */
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break;
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case 0x21:
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/* initialization mode operation */
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if (BX_PIC_THIS s.master_pic.init.in_init) {
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switch (BX_PIC_THIS s.master_pic.init.byte_expected) {
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case 2:
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BX_PIC_THIS s.master_pic.interrupt_offset = value & 0xf8;
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BX_PIC_THIS s.master_pic.init.byte_expected = 3;
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if (bx_dbg.pic) {
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BX_INFO(("pic:master: init command 2 = %02x", (unsigned) value));
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BX_INFO((" offset = INT %02x",
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BX_PIC_THIS s.master_pic.interrupt_offset));
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}
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return;
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break;
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case 3:
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if (bx_dbg.pic)
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BX_INFO(("pic:master: init command 3 = %02x", (unsigned) value));
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if (BX_PIC_THIS s.master_pic.init.requires_4) {
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BX_PIC_THIS s.master_pic.init.byte_expected = 4;
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}
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else {
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BX_PIC_THIS s.master_pic.init.in_init = 0;
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}
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return;
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break;
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case 4:
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if (bx_dbg.pic) {
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BX_INFO(("pic:master: init command 4 = %02x", (unsigned) value));
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if (value & 0x02) BX_INFO((" auto EOI"));
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else BX_INFO(("normal EOI interrupt"));
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}
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if (value & 0x01) {
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if (bx_dbg.pic)
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BX_INFO((" 80x86 mode"));
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} else
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BX_PANIC((" not 80x86 mode"));
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BX_PIC_THIS s.master_pic.init.in_init = 0;
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return;
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break;
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default:
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BX_PANIC(("pic:master expecting bad init command"));
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}
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}
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/* normal operation */
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if (bx_dbg.pic)
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BX_INFO(("setting master pic IMR to %02x", value));
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BX_PIC_THIS s.master_pic.imr = value;
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service_master_pic();
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return;
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break;
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case 0xA0:
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if (value & 0x10) { /* initialization command 1 */
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BX_DEBUG(("slave: init command 1 found"));
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BX_DEBUG((" requires 4 = %u",
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(unsigned) (value & 0x01) ));
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BX_DEBUG((" cascade mode: [0=cascade,1=single] %u",
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(unsigned) ((value & 0x02) >> 1)));
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BX_PIC_THIS s.slave_pic.init.in_init = 1;
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BX_PIC_THIS s.slave_pic.init.requires_4 = (value & 0x01);
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BX_PIC_THIS s.slave_pic.init.byte_expected = 2; /* operation command 2 */
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BX_PIC_THIS s.slave_pic.imr = 0xFF; /* all IRQ's initially masked */
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BX_PIC_THIS s.slave_pic.isr = 0x00; /* no IRQ's in service */
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BX_PIC_THIS s.slave_pic.irr = 0x00; /* no IRQ's requested */
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BX_PIC_THIS s.slave_pic.INT = 0; /* reprogramming clears previous INTR request */
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if ( (value & 0x02) == 1 )
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BX_PANIC(("slave: init command: single mode"));
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return;
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}
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if ( (value & 0x18) == 0x08 ) { /* OCW3 */
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Bit8u special_mask, poll, read_op;
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special_mask = (value & 0x60) >> 5;
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poll = (value & 0x04) >> 2;
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read_op = (value & 0x03);
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if (poll)
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BX_PANIC(("slave:OCW3: poll bit set"));
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if (read_op == 0x02) /* read IRR */
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BX_PIC_THIS s.slave_pic.read_reg_select = 0;
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else if (read_op == 0x03) /* read ISR */
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BX_PIC_THIS s.slave_pic.read_reg_select = 1;
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if (special_mask == 0x02) { /* cancel special mask */
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BX_PIC_THIS s.slave_pic.special_mask = 0;
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}
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else if (special_mask == 0x03) { /* set specific mask */
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BX_PIC_THIS s.slave_pic.special_mask = 1;
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service_slave_pic();
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BX_ERROR(("Congratulations, you found a test case for bug [ #468340 ] pic:slave: OCW3 not implemented. The bug has been fixed, but Bryce needs a way to test it. Please report exactly how you got to this point. It is perfectly safe to continue."));
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}
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return;
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}
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switch (value) {
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case 0x0A: /* select read interrupt request register */
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BX_PIC_THIS s.slave_pic.read_reg_select = 0;
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break;
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case 0x0B: /* select read interrupt in-service register */
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BX_PIC_THIS s.slave_pic.read_reg_select = 1;
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break;
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case 0x20: /* end of interrupt command */
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/* clear highest current in service bit */
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for (irq=0; irq<=7; irq++) {
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if (BX_PIC_THIS s.slave_pic.isr & (1 << irq)) {
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BX_PIC_THIS s.slave_pic.isr &= ~(1 << irq);
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break; /* out of for loop */
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}
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}
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service_slave_pic();
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break;
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|
case 0x60: /* specific EOI 0 */
|
|
case 0x61: /* specific EOI 1 */
|
|
case 0x62: /* specific EOI 2 */
|
|
case 0x63: /* specific EOI 3 */
|
|
case 0x64: /* specific EOI 4 */
|
|
case 0x65: /* specific EOI 5 */
|
|
case 0x66: /* specific EOI 6 */
|
|
case 0x67: /* specific EOI 7 */
|
|
BX_PIC_THIS s.slave_pic.isr &= ~(1 << (value-0x60));
|
|
BX_PIC_THIS s.slave_pic.irr &= ~(1 << (value-0x60));
|
|
service_slave_pic();
|
|
break;
|
|
|
|
// IRQ lowest priority commands
|
|
case 0xC0: // 0 7 6 5 4 3 2 1
|
|
case 0xC1: // 1 0 7 6 5 4 3 2
|
|
case 0xC2: // 2 1 0 7 6 5 4 3
|
|
case 0xC3: // 3 2 1 0 7 6 5 4
|
|
case 0xC4: // 4 3 2 1 0 7 6 5
|
|
case 0xC5: // 5 4 3 2 1 0 7 6
|
|
case 0xC6: // 6 5 4 3 2 1 0 7
|
|
case 0xC7: // 7 6 5 4 3 2 1 0
|
|
// ignore for now
|
|
BX_INFO(("IRQ lowest command 0x%x", value));
|
|
break;
|
|
|
|
default:
|
|
BX_PANIC(("PIC: write to port A0h = %02x", value));
|
|
} /* switch (value) */
|
|
break;
|
|
|
|
case 0xA1:
|
|
/* initialization mode operation */
|
|
if (BX_PIC_THIS s.slave_pic.init.in_init) {
|
|
switch (BX_PIC_THIS s.slave_pic.init.byte_expected) {
|
|
case 2:
|
|
BX_PIC_THIS s.slave_pic.interrupt_offset = value & 0xf8;
|
|
BX_PIC_THIS s.slave_pic.init.byte_expected = 3;
|
|
if (bx_dbg.pic) {
|
|
BX_DEBUG(("slave: init command 2 = %02x", (unsigned) value));
|
|
BX_DEBUG((" offset = INT %02x",
|
|
BX_PIC_THIS s.slave_pic.interrupt_offset));
|
|
}
|
|
return;
|
|
break;
|
|
case 3:
|
|
BX_DEBUG(("slave: init command 3 = %02x", (unsigned) value));
|
|
if (BX_PIC_THIS s.slave_pic.init.requires_4) {
|
|
BX_PIC_THIS s.slave_pic.init.byte_expected = 4;
|
|
} else {
|
|
BX_PIC_THIS s.slave_pic.init.in_init = 0;
|
|
}
|
|
return;
|
|
break;
|
|
case 4:
|
|
if (bx_dbg.pic) {
|
|
BX_DEBUG(("slave: init command 4 = %02x", (unsigned) value));
|
|
if (value & 0x02) BX_INFO((" auto EOI"));
|
|
else BX_DEBUG(("normal EOI interrupt"));
|
|
}
|
|
if (value & 0x01) {
|
|
if (bx_dbg.pic)
|
|
BX_INFO((" 80x86 mode"));
|
|
} else BX_PANIC(("not 80x86 mode"));
|
|
BX_PIC_THIS s.slave_pic.init.in_init = 0;
|
|
return;
|
|
break;
|
|
default:
|
|
BX_PANIC(("slave: expecting bad init command"));
|
|
}
|
|
}
|
|
|
|
/* normal operation */
|
|
if (bx_dbg.pic)
|
|
BX_INFO(("setting slave pic IMR to %02x", value));
|
|
BX_PIC_THIS s.slave_pic.imr = value;
|
|
service_slave_pic();
|
|
return;
|
|
break;
|
|
} /* switch (address) */
|
|
|
|
return;
|
|
}
|
|
|
|
void
|
|
bx_pic_c::trigger_irq(unsigned irq_no)
|
|
{
|
|
#if BX_SUPPORT_APIC
|
|
// forward this function call to the ioapic too
|
|
BX_PIC_THIS devices->ioapic->trigger_irq (irq_no, -1);
|
|
#endif
|
|
|
|
int irq_no_bitmask;
|
|
|
|
if ( irq_no > 15 )
|
|
BX_PANIC(("trigger_irq: irq out of range"));
|
|
|
|
if (bx_dbg.pic)
|
|
BX_INFO(("trigger_irq(%d decimal)", (unsigned) irq_no));
|
|
|
|
if (irq_no <= 7) {
|
|
irq_no_bitmask = 1 << irq_no;
|
|
BX_PIC_THIS s.master_pic.irr |= irq_no_bitmask;
|
|
service_master_pic();
|
|
}
|
|
else { // irq = 8..15
|
|
irq_no_bitmask = 1 << (irq_no - 8);
|
|
BX_PIC_THIS s.slave_pic.irr |= irq_no_bitmask;
|
|
service_slave_pic();
|
|
}
|
|
}
|
|
|
|
void
|
|
bx_pic_c::untrigger_irq(unsigned irq_no)
|
|
{
|
|
#if BX_SUPPORT_APIC
|
|
// forward this function call to the ioapic too
|
|
BX_PIC_THIS devices->ioapic->untrigger_irq (irq_no, -1);
|
|
#endif
|
|
|
|
int irq_no_bitmask;
|
|
|
|
if ( irq_no > 15 )
|
|
BX_PANIC(("untrigger_irq: irq out of range"));
|
|
|
|
if (bx_dbg.pic)
|
|
BX_INFO(("untrigger_irq(%d decimal)", (unsigned) irq_no));
|
|
|
|
if (irq_no <= 7) {
|
|
irq_no_bitmask = 1 << irq_no;
|
|
if (BX_PIC_THIS s.master_pic.imr & irq_no_bitmask) {
|
|
BX_PIC_THIS s.master_pic.irr &= ~irq_no_bitmask;
|
|
}
|
|
}
|
|
else { // irq = 8..15
|
|
irq_no_bitmask = 1 << (irq_no - 8);
|
|
if (BX_PIC_THIS s.slave_pic.imr & irq_no_bitmask) {
|
|
BX_PIC_THIS s.slave_pic.irr &= ~irq_no_bitmask;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* */
|
|
void
|
|
bx_pic_c::service_master_pic(void)
|
|
{
|
|
Bit8u unmasked_requests;
|
|
int irq;
|
|
Bit8u isr, max_irq;
|
|
|
|
if (BX_PIC_THIS s.master_pic.INT) { /* last interrupt still not acknowleged */
|
|
return;
|
|
}
|
|
|
|
if (BX_PIC_THIS s.master_pic.special_mask) {
|
|
/* all priorities may be enabled. check all IRR bits except ones
|
|
* which have corresponding ISR bits set
|
|
*/
|
|
max_irq = 7;
|
|
}
|
|
else { /* normal mode */
|
|
/* Find the highest priority IRQ that is enabled due to current ISR */
|
|
isr = BX_PIC_THIS s.master_pic.isr;
|
|
if (isr) {
|
|
max_irq = 0;
|
|
while ( (isr & 0x01) == 0 ) {
|
|
isr >>= 1;
|
|
max_irq++;
|
|
}
|
|
if (max_irq == 0 ) return; /* IRQ0 in-service, no other priorities allowed */
|
|
if (max_irq > 7) BX_PANIC(("error in service_master_pic()"));
|
|
}
|
|
else
|
|
max_irq = 7; /* 0..7 bits in ISR are cleared */
|
|
}
|
|
|
|
|
|
/* now, see if there are any higher priority requests */
|
|
if ((unmasked_requests = (BX_PIC_THIS s.master_pic.irr & ~BX_PIC_THIS s.master_pic.imr)) ) {
|
|
for (irq=0; irq<=max_irq; irq++) {
|
|
/* for special mode, since we're looking at all IRQ's, skip if
|
|
* current IRQ is already in-service
|
|
*/
|
|
if ( BX_PIC_THIS s.master_pic.special_mask && ((BX_PIC_THIS s.master_pic.isr >> irq) & 0x01) )
|
|
continue;
|
|
if (unmasked_requests & (1 << irq)) {
|
|
BX_DEBUG(("signalling IRQ(%u)", (unsigned) irq));
|
|
BX_PIC_THIS s.master_pic.irr &= ~(1 << irq);
|
|
/*??? do for slave too: BX_PIC_THIS s.master_pic.isr |= (1 << irq);*/
|
|
BX_PIC_THIS s.master_pic.INT = 1;
|
|
BX_SET_INTR(1);
|
|
BX_PIC_THIS s.master_pic.irq = irq;
|
|
return;
|
|
} /* if (unmasked_requests & ... */
|
|
} /* for (irq=7 ... */
|
|
} /* if (unmasked_requests = ... */
|
|
}
|
|
|
|
|
|
void
|
|
bx_pic_c::service_slave_pic(void)
|
|
{
|
|
Bit8u unmasked_requests;
|
|
int irq;
|
|
Bit8u isr, lowest_priority_irq;
|
|
|
|
if (BX_PIC_THIS s.slave_pic.INT) { /* last interrupt still not acknowleged */
|
|
return;
|
|
}
|
|
|
|
if (BX_PIC_THIS s.master_pic.special_mask) {
|
|
/* all priorities may be enabled. check all IRR bits except ones
|
|
* which have corresponding ISR bits set
|
|
*/
|
|
lowest_priority_irq = 8;
|
|
}
|
|
else {
|
|
/* Find the highest priority IRQ that is enabled due to current ISR */
|
|
isr = BX_PIC_THIS s.slave_pic.isr;
|
|
if (isr) {
|
|
lowest_priority_irq = 0;
|
|
while ( !(isr & 0x01) ) {
|
|
isr >>= 1;
|
|
lowest_priority_irq++;
|
|
}
|
|
if (lowest_priority_irq > 7) BX_PANIC(("error in service_slave_pic()"));
|
|
}
|
|
else
|
|
lowest_priority_irq = 8;
|
|
}
|
|
|
|
|
|
/* now, see if there are any higher priority requests */
|
|
if ((unmasked_requests = (BX_PIC_THIS s.slave_pic.irr & ~BX_PIC_THIS s.slave_pic.imr)) ) {
|
|
for (irq=0; irq<lowest_priority_irq; irq++) {
|
|
/* for special mode, since we're looking at all IRQ's, skip if
|
|
* current IRQ is already in-service
|
|
*/
|
|
if ( BX_PIC_THIS s.slave_pic.special_mask && ((BX_PIC_THIS s.slave_pic.isr >> irq) & 0x01) )
|
|
continue;
|
|
if (unmasked_requests & (1 << irq)) {
|
|
if (bx_dbg.pic)
|
|
BX_DEBUG(("slave: signalling IRQ(%u)",
|
|
(unsigned) 8 + irq));
|
|
BX_PIC_THIS s.slave_pic.irr &= ~(1 << irq);
|
|
BX_PIC_THIS s.slave_pic.INT = 1;
|
|
BX_PIC_THIS s.master_pic.irr |= 0x04; /* request IRQ 2 on master pic */
|
|
BX_PIC_THIS s.slave_pic.irq = irq;
|
|
service_master_pic();
|
|
return;
|
|
} /* if (unmasked_requests & ... */
|
|
} /* for (irq=7 ... */
|
|
} /* if (unmasked_requests = ... */
|
|
}
|
|
|
|
|
|
/* CPU handshakes with PIC after acknowledging interrupt */
|
|
Bit8u
|
|
bx_pic_c::IAC(void)
|
|
{
|
|
Bit8u vector;
|
|
Bit8u irq;
|
|
|
|
BX_SET_INTR(0);
|
|
BX_PIC_THIS s.master_pic.INT = 0;
|
|
BX_PIC_THIS s.master_pic.isr |= (1 << BX_PIC_THIS s.master_pic.irq);
|
|
BX_PIC_THIS s.master_pic.irr &= ~(1 << BX_PIC_THIS s.master_pic.irq);
|
|
|
|
if (BX_PIC_THIS s.master_pic.irq != 2) {
|
|
irq = BX_PIC_THIS s.master_pic.irq;
|
|
vector = irq + BX_PIC_THIS s.master_pic.interrupt_offset;
|
|
}
|
|
else { /* IRQ2 = slave pic IRQ8..15 */
|
|
BX_PIC_THIS s.slave_pic.INT = 0;
|
|
irq = BX_PIC_THIS s.slave_pic.irq;
|
|
vector = irq + BX_PIC_THIS s.slave_pic.interrupt_offset;
|
|
BX_PIC_THIS s.slave_pic.isr |= (1 << BX_PIC_THIS s.slave_pic.irq);
|
|
BX_PIC_THIS s.slave_pic.irr &= ~(1 << BX_PIC_THIS s.slave_pic.irq);
|
|
service_slave_pic();
|
|
irq += 8; // for debug printing purposes
|
|
}
|
|
|
|
service_master_pic();
|
|
|
|
BX_DBG_IAC_REPORT(vector, irq);
|
|
return(vector);
|
|
}
|
|
|
|
void
|
|
bx_pic_c::show_pic_state(void)
|
|
{
|
|
BX_INFO(("s.master_pic.imr = %02x", BX_PIC_THIS s.master_pic.imr));
|
|
BX_INFO(("s.master_pic.isr = %02x", BX_PIC_THIS s.master_pic.isr));
|
|
BX_INFO(("s.master_pic.irr = %02x", BX_PIC_THIS s.master_pic.irr));
|
|
BX_INFO(("s.master_pic.irq = %02x", BX_PIC_THIS s.master_pic.irq));
|
|
}
|