7cae4b94c4
With this patch the INVLPG instruction doesn't invalidate the whole TLB, but only a single page table entry.
68 lines
2.2 KiB
Plaintext
68 lines
2.2 KiB
Plaintext
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Patch name: patch.invlpg-tlb-tweggen
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Author: Timo Weggen
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Date: 06 August 2002
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Detailed description:
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With this patch the INVLPG instruction doesn't invalidate the
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whole TLB, but only a single page table entry.
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'during test with my experimental kernel, I encoutered
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massive performance drawbacks during my uKernel's
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message passing implementation.
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After grepping through bochs-developers I now assume,
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the use of the invlpg instruction could be the point.'
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Patch was created with:
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cvs diff -u
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Apply patch to what version:
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cvs checked out on 06 August 2002
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Instructions:
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To patch, go to main bochs directory.
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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Index: config.h.in
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===================================================================
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RCS file: /cvsroot/bochs/bochs/config.h.in,v
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retrieving revision 1.50
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diff -u -r1.50 config.h.in
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--- config.h.in 5 Jun 2002 03:59:30 -0000 1.50
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+++ config.h.in 6 Aug 2002 08:57:11 -0000
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@@ -140,6 +140,8 @@
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// There will be a many-to-one mapping to each TLB cache slot.
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// When there are collisions, the old entry is overwritten with
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// one for the newest access.
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+// BX_TLB_ENTRY_FLUSH : controls whether the INVLPG instruction
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+// invalidates a single page table entry or the whole TLB
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#define BX_SUPPORT_PAGING 1
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#define BX_USE_TLB 1
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@@ -147,6 +149,7 @@
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#define BX_TLB_SIZE 1024
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#define BX_TLB_INDEX_OF(lpf) (((lpf) & 0x003ff000) >> 12)
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+#define BX_TLB_ENTRY_FLUSH 1
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// Compile in support for DMA & FLOPPY IO. You'll need this
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// if you plan to use the floppy drive emulation. But if
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Index: cpu/paging.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/paging.cc,v
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retrieving revision 1.9
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diff -u -r1.9 paging.cc
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--- cpu/paging.cc 19 Jun 2002 15:49:07 -0000 1.9
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+++ cpu/paging.cc 6 Aug 2002 08:57:11 -0000
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@@ -445,8 +445,12 @@
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}
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#if BX_USE_TLB
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+#if BX_TLB_ENTRY_FLUSH
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+ BX_CPU_THIS_PTR TLB.entry[BX_TLB_INDEX_OF(i->rm_addr)].lpf = BX_INVALID_TLB_ENTRY;
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+#else
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// Just clear the entire TLB, ugh!
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TLB_clear();
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+#endif
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#endif // BX_USE_TLB
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BX_INSTR_TLB_CNTRL(BX_INSTR_INVLPG, 0);
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