148 lines
14 KiB
C
148 lines
14 KiB
C
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2023 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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x86_feature(BX_ISA_386, "386ni") /* 386 or earlier instruction */
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x86_feature(BX_ISA_X87, "x87") /* FPU (x87) instruction */
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x86_feature(BX_ISA_486, "486ni") /* 486 new instruction */
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x86_feature(BX_ISA_PENTIUM, "pentium_ni") /* Pentium new instruction */
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x86_feature(BX_ISA_P6, "p6ni") /* P6 new instruction */
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x86_feature(BX_ISA_MMX, "mmx") /* MMX instruction */
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x86_feature(BX_ISA_3DNOW, "3dnow") /* 3DNow! instruction (AMD) */
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x86_feature(BX_ISA_DEBUG_EXTENSIONS, "debugext") /* Debug Extensions support */
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x86_feature(BX_ISA_VME, "vme") /* VME support */
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x86_feature(BX_ISA_PSE, "pse") /* PSE support */
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x86_feature(BX_ISA_PAE, "pae") /* PAE support */
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x86_feature(BX_ISA_PGE, "pge") /* Global Pages support */
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x86_feature(BX_ISA_PSE36, "pse36") /* PSE-36 support */
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x86_feature(BX_ISA_MTRR, "mtrr") /* MTRR support */
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x86_feature(BX_ISA_PAT, "pat") /* PAT support */
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x86_feature(BX_ISA_SYSCALL_SYSRET_LEGACY, "legacy_syscall_sysret") /* SYSCALL/SYSRET in legacy mode (AMD) */
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x86_feature(BX_ISA_SYSENTER_SYSEXIT, "sysenter_sysexit") /* SYSENTER/SYSEXIT instruction */
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x86_feature(BX_ISA_CLFLUSH, "clflush") /* CLFLUSH instruction */
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x86_feature(BX_ISA_CLFLUSHOPT, "clflushopt") /* CLFLUSHOPT instruction */
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x86_feature(BX_ISA_CLWB, "clwb") /* CLWB instruction */
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x86_feature(BX_ISA_CLDEMOTE, "cldemote") /* CLDEMOTE instruction */
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x86_feature(BX_ISA_SSE, "sse") /* SSE instruction */
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x86_feature(BX_ISA_SSE2, "sse2") /* SSE2 instruction */
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x86_feature(BX_ISA_SSE3, "sse3") /* SSE3 instruction */
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x86_feature(BX_ISA_SSSE3, "ssse3") /* SSSE3 instruction */
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x86_feature(BX_ISA_SSE4_1, "sse4_1") /* SSE4_1 instruction */
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x86_feature(BX_ISA_SSE4_2, "sse4_2") /* SSE4_2 instruction */
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x86_feature(BX_ISA_POPCNT, "popcnt") /* POPCNT instruction */
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x86_feature(BX_ISA_MONITOR_MWAIT, "mwait") /* MONITOR/MWAIT instruction */
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x86_feature(BX_ISA_WAITPKG, "waitpkg") /* TPAUSE/UMONITOR/UMWAIT instructions */
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x86_feature(BX_ISA_MONITORLESS_MWAIT, "monitorless_mwait") /* MONITOR-less MWAIT extension */
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x86_feature(BX_ISA_MONITORX_MWAITX, "mwaitx") /* MONITORX/MWAITX instruction (AMD) */
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x86_feature(BX_ISA_VMX, "vmx") /* VMX instruction */
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x86_feature(BX_ISA_SMX, "smx") /* SMX instruction */
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x86_feature(BX_ISA_LONG_MODE, "longmode") /* Long Mode (x86-64) support */
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x86_feature(BX_ISA_LM_LAHF_SAHF, "lm_lahf_sahf") /* Long Mode LAHF/SAHF instruction */
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x86_feature(BX_ISA_NX, "nx") /* No-Execute Pages support */
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x86_feature(BX_ISA_1G_PAGES, "1g_pages") /* 1Gb pages support */
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x86_feature(BX_ISA_CMPXCHG16B, "cmpxhg16b") /* CMPXCHG16B instruction */
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x86_feature(BX_ISA_RDTSCP, "rdtscp") /* RDTSCP instruction */
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x86_feature(BX_ISA_FFXSR, "ffxsr") /* EFER.FFXSR support (AMD) */
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x86_feature(BX_ISA_XSAVE, "xsave") /* XSAVE/XRSTOR extensions instruction */
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x86_feature(BX_ISA_XSAVEOPT, "xsaveopt") /* XSAVEOPT instruction */
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x86_feature(BX_ISA_XSAVEC, "xsavec") /* XSAVEC instruction */
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x86_feature(BX_ISA_XSAVES, "xsaves") /* XSAVES instruction */
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x86_feature(BX_ISA_AES_PCLMULQDQ, "aes_pclmulqdq") /* AES+PCLMULQDQ instructions */
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x86_feature(BX_ISA_VAES_VPCLMULQDQ, "vaes_vpclmulqdq") /* Wide vector versions of AES+PCLMULQDQ instructions */
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x86_feature(BX_ISA_MOVBE, "movbe") /* MOVBE instruction */
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x86_feature(BX_ISA_FSGSBASE, "fsgsbase") /* FS/GS BASE access instruction */
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x86_feature(BX_ISA_INVPCID, "invpcid") /* INVPCID instruction */
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x86_feature(BX_ISA_AVX, "avx") /* AVX instruction */
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x86_feature(BX_ISA_AVX2, "avx2") /* AVX2 instruction */
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x86_feature(BX_ISA_AVX_F16C, "avx_f16c") /* AVX F16 convert instruction */
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x86_feature(BX_ISA_AVX_FMA, "avx_fma") /* AVX FMA instruction */
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x86_feature(BX_ISA_ALT_MOV_CR8, "altmovcr8") /* LOCK CR0 access CR8 (AMD) */
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x86_feature(BX_ISA_SSE4A, "sse4a") /* SSE4A instruction (AMD) */
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x86_feature(BX_ISA_MISALIGNED_SSE, "misaligned_sse") /* Misaligned SSE (AMD) */
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x86_feature(BX_ISA_LZCNT, "lzcnt") /* LZCNT instruction */
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x86_feature(BX_ISA_BMI1, "bmi1") /* BMI1 instruction */
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x86_feature(BX_ISA_BMI2, "bmi2") /* BMI2 instruction */
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x86_feature(BX_ISA_FMA4, "fma4") /* FMA4 instruction (AMD) */
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x86_feature(BX_ISA_XOP, "xop") /* XOP instruction (AMD) */
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x86_feature(BX_ISA_TBM, "tbm") /* TBM instruction (AMD) */
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x86_feature(BX_ISA_SVM, "svm") /* SVM instruction (AMD) */
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x86_feature(BX_ISA_RDRAND, "rdrand") /* RDRAND instruction */
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x86_feature(BX_ISA_RDSEED, "rdseed") /* RDSEED instruction */
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x86_feature(BX_ISA_ADX, "adx") /* ADCX/ADOX instruction */
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x86_feature(BX_ISA_SMAP, "smap") /* SMAP support */
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x86_feature(BX_ISA_SHA, "sha") /* SHA instruction */
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x86_feature(BX_ISA_SHA512, "sha512") /* SHA-512 instruction */
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x86_feature(BX_ISA_GFNI, "gfni") /* GFNI instruction */
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x86_feature(BX_ISA_SM3, "sm3") /* SM3 instruction */
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x86_feature(BX_ISA_SM4, "sm4") /* SM4 instruction */
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x86_feature(BX_ISA_AVX512, "avx512") /* AVX-512 instruction */
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x86_feature(BX_ISA_AVX512_DQ, "avx512dq") /* AVX-512DQ instruction */
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x86_feature(BX_ISA_AVX512_BW, "avx512bw") /* AVX-512 Byte/Word instruction */
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x86_feature(BX_ISA_AVX512_CD, "avx512cd") /* AVX-512 Conflict Detection instruction */
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x86_feature(BX_ISA_AVX512_PF, "avx512pf") /* AVX-512 Sparse Prefetch instruction */
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x86_feature(BX_ISA_AVX512_ER, "avx512er") /* AVX-512 Exponential/Reciprocal instruction */
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x86_feature(BX_ISA_AVX512_VBMI, "avx512vbmi") /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
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x86_feature(BX_ISA_AVX512_VBMI2, "avx512vbmi2") /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
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x86_feature(BX_ISA_AVX512_IFMA52, "avx512ifma52") /* AVX-512 IFMA52 Instructions */
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x86_feature(BX_ISA_AVX512_VPOPCNTDQ, "avx512vpopcnt") /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
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x86_feature(BX_ISA_AVX512_VNNI, "avx512vnni") /* AVX-512 VNNI Instructions */
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x86_feature(BX_ISA_AVX512_BITALG, "avx512bitalg") /* AVX-512 BITALG Instructions */
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x86_feature(BX_ISA_AVX512_VP2INTERSECT, "avx512vp2intersect") /* AVX-512 VP2INTERSECT Instructions */
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x86_feature(BX_ISA_AVX512_BF16, "avx512bf16") /* AVX-512 BF16 Instructions */
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x86_feature(BX_ISA_AVX512_FP16, "avx512fp16") /* AVX-512 FP16 Instructions */
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x86_feature(BX_ISA_AVX_IFMA, "avx_ifma") /* AVX encoded IFMA Instructions */
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x86_feature(BX_ISA_AVX_VNNI, "avx_vnni") /* AVX encoded VNNI Instructions */
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x86_feature(BX_ISA_AVX_VNNI_INT8, "avx_vnni_int8") /* AVX encoded VNNI-INT8 Instructions */
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x86_feature(BX_ISA_AVX_VNNI_INT16, "avx_vnni_int16") /* AVX encoded VNNI-INT16 Instructions */
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x86_feature(BX_ISA_AVX_NE_CONVERT, "avx_ne_convert") /* AVX-NE-CONVERT Instructions */
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x86_feature(BX_ISA_AMX, "amx") /* AMX Instructions */
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x86_feature(BX_ISA_AMX_INT8, "amx_int8") /* AMX-INT8 Instructions */
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x86_feature(BX_ISA_AMX_BF16, "amx_bf16") /* AMX-BF16 Instructions */
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x86_feature(BX_ISA_AMX_FP16, "amx_fp16") /* AMX-FP16 Instructions */
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x86_feature(BX_ISA_AMX_COMPLEX, "amx_complex") /* AMX-COMPLEX Instructions */
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x86_feature(BX_ISA_XAPIC, "xapic") /* XAPIC support */
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x86_feature(BX_ISA_X2APIC, "x2apic") /* X2APIC support */
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x86_feature(BX_ISA_XAPIC_EXT, "xapicext") /* XAPIC Extensions support (AMD) */
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x86_feature(BX_ISA_PCID, "pcid") /* PCID support */
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x86_feature(BX_ISA_SMEP, "smep") /* SMEP support */
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x86_feature(BX_ISA_TSC_ADJUST, "tsc_adjust") /* TSC-Adjust MSR */
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x86_feature(BX_ISA_TSC_DEADLINE, "tsc_deadline") /* TSC-Deadline */
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x86_feature(BX_ISA_FOPCODE_DEPRECATION, "fopcode_deprecation") /* FOPCODE Deprecation - FOPCODE update on unmasked x87 exception only */
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x86_feature(BX_ISA_FCS_FDS_DEPRECATION, "fcs_fds_deprecation") /* FCS/FDS Deprecation */
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x86_feature(BX_ISA_FDP_DEPRECATION, "fdp_deprecation") /* FDP Deprecation - FDP update on unmasked x87 exception only */
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x86_feature(BX_ISA_PKU, "pku") /* User-Mode Protection Keys */
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x86_feature(BX_ISA_PKS, "pks") /* Supervisor-Mode Protection Keys */
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x86_feature(BX_ISA_UMIP, "umip") /* User-Mode Instructions Prevention */
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x86_feature(BX_ISA_RDPID, "rdpid") /* RDPID Support */
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x86_feature(BX_ISA_TCE, "tce") /* Translation Cache Extensions (TCE) support (AMD) */
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x86_feature(BX_ISA_CLZERO, "clzero") /* CLZERO instruction support (AMD) */
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x86_feature(BX_ISA_SCA_MITIGATIONS, "sca_mitigations") /* Report SCA Mitigations in CPUID */
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x86_feature(BX_ISA_CET, "cet") /* Control Flow Enforcement */
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x86_feature(BX_ISA_WRMSRNS, "wrmsrns") /* Non-Serializing version of WRMSR */
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x86_feature(BX_ISA_CMPCCXADD, "cmpccxadd") /* CMPccXADD instructions */
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x86_feature(BX_ISA_SERIALIZE, "serialize") /* SERIALIZE instruction */
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x86_feature(BX_ISA_LASS, "lass") /* Linear Address Space Separation support */
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x86_feature(BX_ISA_LA57, "la57") /* 57-bit Virtual Address and 5-level paging support */
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x86_feature(BX_ISA_UINTR, "uintr") /* User Level Interrupts support */
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x86_feature(BX_ISA_FLEXIBLE_UIRET, "flexible_uiret") /* Flexible UIRET support */
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x86_feature(BX_ISA_MOVDIRI, "movdiri") /* MOVDIRI instruction support */
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x86_feature(BX_ISA_MOVDIR64B, "movdir64b") /* MOVDIR64B instruction support */
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x86_feature(BX_ISA_MSRLIST, "msrlist") /* RDMSRLIST/WRMSRLIST instructions support */
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