d9fc472ba7
Fixed possible RSP corruption in SMP mode - the speculative_rsp variable might be not reset properly
221 lines
7.4 KiB
C++
221 lines
7.4 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2006-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#if BX_INSTRUMENTATION
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class bxInstruction_c;
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// define if you want to store instruction opcode bytes in bxInstruction_c
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#define BX_INSTR_STORE_OPCODE_BYTES
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void bx_instr_init_env(void);
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void bx_instr_exit_env(void);
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void bx_instr_initialize(unsigned cpu);
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// maximum size of an instruction
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#define MAX_OPCODE_LENGTH 16
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// maximum physical addresses an instruction can generate
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#define MAX_DATA_ACCESSES 1024
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class bxInstrumentation {
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public:
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bx_bool ready; // is current instruction ready to be printed
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bx_bool active;
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unsigned cpu_id;
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/* decoding */
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unsigned opcode_length;
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Bit8u opcode[MAX_OPCODE_LENGTH];
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bx_bool is32, is64;
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/* memory accesses */
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unsigned num_data_accesses;
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struct {
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bx_address laddr; // linear address
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bx_phy_address paddr; // physical address
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unsigned rw; // BX_READ, BX_WRITE or BX_RW
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unsigned size; // 1 .. 32
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} data_access[MAX_DATA_ACCESSES];
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/* branch resolution and target */
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bx_bool is_branch;
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bx_bool is_taken;
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bx_address target_linear;
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public:
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bxInstrumentation(): ready(0), active(0) {}
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void set_cpu_id(unsigned cpu) { cpu_id = cpu; }
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void activate() { active = 1; }
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void deactivate() { active = 0; }
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void toggle_active() { active = !active; }
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bx_bool is_active() const { return active; }
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void bx_instr_reset(unsigned type);
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void bx_instr_cnear_branch_taken(bx_address branch_eip, bx_address new_eip);
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void bx_instr_cnear_branch_not_taken(bx_address branch_eip);
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void bx_instr_ucnear_branch(unsigned what, bx_address branch_eip, bx_address new_eip);
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void bx_instr_far_branch(unsigned what, Bit16u new_cs, bx_address new_eip);
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void bx_instr_before_execution(bxInstruction_c *i);
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void bx_instr_after_execution(bxInstruction_c *i);
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void bx_instr_interrupt(unsigned vector);
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void bx_instr_exception(unsigned vector, unsigned error_code);
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void bx_instr_hwinterrupt(unsigned vector, Bit16u cs, bx_address eip);
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void bx_instr_lin_access(bx_address lin, bx_phy_address phy, unsigned len, unsigned rw);
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private:
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void branch_taken(bx_address new_eip);
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void bx_print_instruction(void);
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};
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void bx_instr_init(unsigned cpu);
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extern bxInstrumentation *icpu;
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/* initialization/deinitialization of instrumentalization*/
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#define BX_INSTR_INIT_ENV() bx_instr_init_env()
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#define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
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/* simulation init, shutdown, reset */
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#define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id)
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#define BX_INSTR_EXIT(cpu_id)
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#define BX_INSTR_RESET(cpu_id, type) icpu[cpu_id].bx_instr_reset(type)
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#define BX_INSTR_HLT(cpu_id)
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#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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/* called from command line debugger */
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#define BX_INSTR_DEBUG_PROMPT()
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#define BX_INSTR_DEBUG_CMD(cmd)
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/* branch resolution */
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#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, branch_eip, new_eip) icpu[cpu_id].bx_instr_cnear_branch_taken(branch_eip, new_eip)
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#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id, branch_eip) icpu[cpu_id].bx_instr_cnear_branch_not_taken(branch_eip)
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#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, branch_eip, new_eip) icpu[cpu_id].bx_instr_ucnear_branch(what, branch_eip, new_eip)
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#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) icpu[cpu_id].bx_instr_far_branch(what, new_cs, new_eip)
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/* decoding completed */
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#define BX_INSTR_OPCODE(cpu_id, i, opcode, len, is32, is64)
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/* exceptional case and interrupt */
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#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code) \
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icpu[cpu_id].bx_instr_exception(vector, error_code)
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#define BX_INSTR_INTERRUPT(cpu_id, vector) icpu[cpu_id].bx_instr_interrupt(vector)
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#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) icpu[cpu_id].bx_instr_hwinterrupt(vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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/* execution */
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#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i) icpu[cpu_id].bx_instr_before_execution(i)
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#define BX_INSTR_AFTER_EXECUTION(cpu_id, i) icpu[cpu_id].bx_instr_after_execution(i)
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#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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/* memory access */
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#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) \
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icpu[cpu_id].bx_instr_lin_access(lin, phy, len, rw)
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#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
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/* feedback from device units */
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#define BX_INSTR_INP(addr, len)
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#define BX_INSTR_INP2(addr, len, val)
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#define BX_INSTR_OUTP(addr, len, val)
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/* wrmsr callback */
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#define BX_INSTR_WRMSR(cpu_id, addr, value)
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/* vmexit callback */
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#define BX_INSTR_VMEXIT(cpu_id, reason, qualification)
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#else // BX_INSTRUMENTATION
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/* initialization/deinitialization of instrumentalization */
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#define BX_INSTR_INIT_ENV()
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#define BX_INSTR_EXIT_ENV()
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/* simulation init, shutdown, reset */
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#define BX_INSTR_INITIALIZE(cpu_id)
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#define BX_INSTR_EXIT(cpu_id)
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#define BX_INSTR_RESET(cpu_id, type)
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#define BX_INSTR_HLT(cpu_id)
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#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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/* called from command line debugger */
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#define BX_INSTR_DEBUG_PROMPT()
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#define BX_INSTR_DEBUG_CMD(cmd)
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/* branch resolution */
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#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, branch_eip, new_eip)
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#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id, branch_eip)
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#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, branch_eip, new_eip)
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#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
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/* decoding completed */
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#define BX_INSTR_OPCODE(cpu_id, i, opcode, len, is32, is64)
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/* exceptional case and interrupt */
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#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code)
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#define BX_INSTR_INTERRUPT(cpu_id, vector)
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#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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/* execution */
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#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
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#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
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#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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/* linear memory access */
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#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
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/* physical memory access */
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#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
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/* feedback from device units */
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#define BX_INSTR_INP(addr, len)
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#define BX_INSTR_INP2(addr, len, val)
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#define BX_INSTR_OUTP(addr, len, val)
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/* wrmsr callback */
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#define BX_INSTR_WRMSR(cpu_id, addr, value)
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/* vmexit callback */
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#define BX_INSTR_VMEXIT(cpu_id, reason, qualification)
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#endif // BX_INSTRUMENTATION
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