d4688e8b95
for CPU emulation performance reasons, the alignment check compilation
still can be enabled using configure option --enable-alignment-check.
There is no software in the world which enable #AC exception checking, this
x86 feature is completely legacy but its emulation support costs up to 3-5%
emulation speed.
The checking for #AC exception enable still will be done, if
CPL == 3, EFLAGS.AC = 1 and CR0.AM = 1
but the alignment check is not compiled in, the Bochs will PANIC with corresponding message.
You can press 'always continue' and ignore the PANIC, the simulation will continue as if alignment checking is not enabled.
266 lines
8.4 KiB
C++
266 lines
8.4 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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//
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// Notes:
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//
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// The high bits of the 32bit eip image are ignored by
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// the IRET to VM. The high bits of the 32bit esp image
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// are loaded into ESP. A subsequent push uses
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// only the low 16bits since it's in VM. In neither case
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// did a protection fault occur during actual tests. This
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// is contrary to the Intel docs which claim a #GP for
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// eIP out of code limits.
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//
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// IRET to VM does affect IOPL, IF, VM, and RF
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//
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#if BX_CPU_LEVEL >= 3
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void BX_CPU_C::stack_return_to_v86(Bit32u new_eip, Bit32u raw_cs_selector, Bit32u flags32)
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{
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Bit32u temp_ESP, new_esp;
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Bit16u raw_es_selector, raw_ds_selector, raw_fs_selector,
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raw_gs_selector, raw_ss_selector;
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// Must be 32bit effective opsize, VM is set in upper 16bits of eFLAGS
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// and CPL = 0 to get here
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// ----------------
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// | | OLD GS | eSP+32
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// | | OLD FS | eSP+28
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// | | OLD DS | eSP+24
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// | | OLD ES | eSP+20
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// | | OLD SS | eSP+16
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// | OLD ESP | eSP+12
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// | OLD EFLAGS | eSP+8
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// | | OLD CS | eSP+4
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// | OLD EIP | eSP+0
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// ----------------
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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temp_ESP = ESP;
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else
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temp_ESP = SP;
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// load SS:ESP from stack
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new_esp = stack_read_dword(temp_ESP+12);
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raw_ss_selector = (Bit16u) stack_read_dword(temp_ESP+16);
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// load ES,DS,FS,GS from stack
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raw_es_selector = (Bit16u) stack_read_dword(temp_ESP+20);
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raw_ds_selector = (Bit16u) stack_read_dword(temp_ESP+24);
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raw_fs_selector = (Bit16u) stack_read_dword(temp_ESP+28);
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raw_gs_selector = (Bit16u) stack_read_dword(temp_ESP+32);
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writeEFlags(flags32, EFlagsValidMask);
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// load CS:IP from stack; already read and passed as args
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = raw_cs_selector;
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EIP = new_eip & 0xffff;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = raw_es_selector;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = raw_ds_selector;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = raw_fs_selector;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = raw_gs_selector;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = raw_ss_selector;
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ESP = new_esp; // full 32 bit are loaded
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init_v8086_mode();
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}
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#if BX_CPU_LEVEL >= 5
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#define BX_CR4_VME_ENABLED (BX_CPU_THIS_PTR cr4.get_VME())
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#else
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#define BX_CR4_VME_ENABLED (0)
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#endif
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void BX_CPU_C::iret16_stack_return_from_v86(bxInstruction_c *i)
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{
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if ((BX_CPU_THIS_PTR get_IOPL() < 3) && (BX_CR4_VME_ENABLED == 0)) {
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// trap to virtual 8086 monitor
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BX_DEBUG(("IRET in vm86 with IOPL != 3, VME = 0"));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit16u ip, cs_raw, flags16;
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ip = pop_16();
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cs_raw = pop_16();
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flags16 = pop_16();
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME() && BX_CPU_THIS_PTR get_IOPL() < 3)
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{
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if (((flags16 & EFlagsIFMask) && BX_CPU_THIS_PTR get_VIP()) ||
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(flags16 & EFlagsTFMask))
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{
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BX_DEBUG(("iret16_stack_return_from_v86(): #GP(0) in VME mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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EIP = (Bit32u) ip;
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// IF, IOPL unchanged, EFLAGS.VIF = TMP_FLAGS.IF
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Bit32u changeMask = EFlagsOSZAPCMask | EFlagsTFMask |
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EFlagsDFMask | EFlagsNTMask | EFlagsVIFMask;
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Bit32u flags32 = (Bit32u) flags16;
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if (flags16 & EFlagsIFMask) flags32 |= EFlagsVIFMask;
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writeEFlags(flags32, changeMask);
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return;
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}
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#endif
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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EIP = (Bit32u) ip;
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write_flags(flags16, /*IOPL*/ 0, /*IF*/ 1);
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}
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void BX_CPU_C::iret32_stack_return_from_v86(bxInstruction_c *i)
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{
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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// trap to virtual 8086 monitor
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BX_DEBUG(("IRET in vm86 with IOPL != 3, VME = 0"));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u eip, cs_raw, flags32;
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// Build a mask of the following bits:
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// ID,VIP,VIF,AC,VM,RF,x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u change_mask = EFlagsOSZAPCMask | EFlagsTFMask | EFlagsIFMask
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| EFlagsDFMask | EFlagsNTMask | EFlagsRFMask;
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#if BX_CPU_LEVEL >= 4
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change_mask |= (EFlagsIDMask | EFlagsACMask); // ID/AC
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#endif
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eip = pop_32();
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cs_raw = pop_32();
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flags32 = pop_32();
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) cs_raw);
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EIP = eip;
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// VIF, VIP, VM, IOPL unchanged
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writeEFlags(flags32, change_mask);
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}
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int BX_CPU_C::v86_redirect_interrupt(Bit8u vector)
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{
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME())
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{
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bx_address tr_base = BX_CPU_THIS_PTR tr.cache.u.segment.base;
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if (BX_CPU_THIS_PTR tr.cache.u.segment.limit_scaled < 103) {
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BX_ERROR(("v86_redirect_interrupt(): TR.limit < 103 in VME"));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u io_base = system_read_word(tr_base + 102), offset = io_base - 32 + (vector >> 3);
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if (offset > BX_CPU_THIS_PTR tr.cache.u.segment.limit_scaled) {
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BX_ERROR(("v86_redirect_interrupt(): failed to fetch VME redirection bitmap"));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit8u vme_redirection_bitmap = system_read_byte(tr_base + offset);
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if (!(vme_redirection_bitmap & (1 << (vector & 7))))
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{
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// redirect interrupt through virtual-mode idt
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Bit16u temp_flags = (Bit16u) read_eflags();
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Bit16u temp_CS = system_read_word(vector*4 + 2);
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Bit16u temp_IP = system_read_word(vector*4);
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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temp_flags |= EFlagsIOPLMask;
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if (BX_CPU_THIS_PTR get_VIF())
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temp_flags |= EFlagsIFMask;
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else
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temp_flags &= ~EFlagsIFMask;
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}
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Bit16u old_IP = IP;
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Bit16u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
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push_16(temp_flags);
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// push return address onto new stack
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push_16(old_CS);
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push_16(old_IP);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) temp_CS);
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EIP = temp_IP;
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BX_CPU_THIS_PTR clear_TF();
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BX_CPU_THIS_PTR clear_RF();
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if (BX_CPU_THIS_PTR get_IOPL() == 3)
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BX_CPU_THIS_PTR clear_IF();
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else
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BX_CPU_THIS_PTR clear_VIF();
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return 1;
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}
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}
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#endif
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// interrupt is not redirected or VME is OFF
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if (BX_CPU_THIS_PTR get_IOPL() < 3)
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{
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BX_DEBUG(("v86_redirect_interrupt(): interrupt cannot be redirected, generate #GP(0)"));
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exception(BX_GP_EXCEPTION, 0);
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}
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return 0;
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}
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void BX_CPU_C::init_v8086_mode(void)
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{
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for(unsigned sreg = 0; sreg < 6; sreg++) {
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BX_CPU_THIS_PTR sregs[sreg].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
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BX_CPU_THIS_PTR sregs[sreg].cache.p = 1;
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BX_CPU_THIS_PTR sregs[sreg].cache.dpl = 3;
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BX_CPU_THIS_PTR sregs[sreg].cache.segment = 1;
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BX_CPU_THIS_PTR sregs[sreg].cache.type = BX_DATA_READ_WRITE_ACCESSED;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.base =
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BX_CPU_THIS_PTR sregs[sreg].selector.value << 4;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.limit_scaled = 0xffff;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.g = 0;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.d_b = 0;
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BX_CPU_THIS_PTR sregs[sreg].cache.u.segment.avl = 0;
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BX_CPU_THIS_PTR sregs[sreg].selector.rpl = 3;
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}
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handleCpuModeChange();
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#if BX_CPU_LEVEL >= 4
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handleAlignmentCheck(/* CPL change */);
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#endif
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invalidate_stack_cache();
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}
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#endif /* BX_CPU_LEVEL >= 3 */
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