d46a9b7205
- Since the pci_read_handler() method is identical in most devices, move it to the base class to reduce code duplication. Only the 'pcidev' device has it's own implementation (NOTE: it is not maintained yet). - Minor other fixes and cleanups in some PCI devices.
211 lines
6.5 KiB
C++
211 lines
6.5 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2009-2016 Benjamin D Lunt (fys [at] fysnet [dot] net)
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// 2009-2017 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#ifndef BX_IODEV_UHCI_CORE_H
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#define BX_IODEV_UHCI_CORE_H
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#define USB_UHCI_PORTS 2
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typedef struct {
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int timer_index;
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// Registers
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// Base + 0x00 Command register
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// Base + 0x02 Status register
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// Base + 0x04 Interrupt Enable register
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// Base + 0x06 Frame Number register
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// Base + 0x08 Frame Base Register (32-bit)
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// Base + 0x0C Start of Frame Modify register
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// Base + 0x0D
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// Base + 0x0E
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// Base + 0x0F
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// Base + 0x10 Eight(?) 16-bit ports (one for each port on hub)
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// Bit reps of registers above
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// Command Register
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// Bits 15-8 are reserved
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// Bit 7 = Maximum packet size
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// Bit 6 = Host Controller has been configured (set by software)
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// Bit 5 = software debug mode
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// Bit 4 = force global resume
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// Bit 3 = enter global suspend mode
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// Bit 2 = global reset
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// Bit 1 = host controller reset
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// Bit 0 = run/stop schedule
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struct {
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bx_bool max_packet_size; //(bit 7) 0 = 32 bytes, 1 = 64 bytes
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bx_bool configured; //(bit 6)
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bx_bool debug; //(bit 5)
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bx_bool resume; //(bit 4)
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bx_bool suspend; //(bit 3)
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bx_bool reset; //(bit 2)
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bx_bool host_reset; //(bit 1)
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bx_bool schedule; //(bit 0) 0 = Stop, 1 = Run
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} usb_command;
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// Status Register
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// Bits 15-6 are reserved
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// Bit 5 = Host controller halted
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// Bit 4 = Host controller process error
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// Bit 3 = PCI Bus error
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// Bit 2 = resume received
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// Bit 1 = USB error interrupt
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// Bit 0 = USB interrupt
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struct {
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bx_bool host_halted; //(bit 5)
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bx_bool host_error; //(bit 4)
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bx_bool pci_error; //(bit 3)
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bx_bool resume; //(bit 2)
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bx_bool error_interrupt; //(bit 1)
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bx_bool interrupt; //(bit 0)
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Bit8u status2; // bit 0 and 1 are used to generate the interrupt
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} usb_status;
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// Interrupt Enable Register
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// Bits 15-4 are reserved
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// Bit 3 = enable short packet interrupts
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// Bit 2 = enable interrupt On Complete
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// Bit 1 = enable resume
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// Bit 0 = enable timeout/crc
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struct {
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bx_bool short_packet; //(bit 3)
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bx_bool on_complete; //(bit 2)
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bx_bool resume; //(bit 1)
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bx_bool timeout_crc; //(bit 0)
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} usb_enable;
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// Frame Number Register
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// Bits 15-11 are reserved
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// Bits 10-0 Frame List Current Index/Frame Number
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struct {
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Bit16u frame_num;
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} usb_frame_num;
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// Frame List Base Address Register
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// Bits 31-12 Base
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// Bits 11-0 *must* be zeros when written to
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struct {
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Bit32u frame_base;
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} usb_frame_base;
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// Start of Frame Modify Register
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// Bit 7 reserved
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// Bits 6-0 SOF timing value (default 64)
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// SOF cycle time equals 11936+timing value
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struct {
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Bit8u sof_timing;
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} usb_sof;
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// Port Register (0-1)
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// Bits 15-13 are reserved
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// Bit 12 suspend port
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// Bit 11-10 are reserved
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// Bit 9 port in reset state
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// Bit 8 low-speed device is attached (read-only)
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// Bit 7 reserved
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// Bit 6 resume detected (read-only)
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// Bit 5 line-status D+ (read-only)
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// Bit 4 line-status D- (read-only)
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// Bit 3 port enabled/disable status has changed
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// (write 1 to this bit to clear it)
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// Bit 2 port is enabled
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// Bit 1 connect status has changed
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// (write 1 to this bit to clear it)
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// Bit 0 current connect status (read-only)
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// Can only write in WORD sizes (Read in byte sizes???)
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struct {
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// our data
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usb_device_c *device; // device connected to this port
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// bit reps of actual port
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bx_bool suspend;
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bx_bool reset;
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bx_bool low_speed;
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bx_bool resume;
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bx_bool line_dminus;
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bx_bool line_dplus;
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bx_bool able_changed;
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bx_bool enabled;
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bx_bool connect_changed;
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bx_bool status;
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} usb_port[USB_UHCI_PORTS];
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Bit8u devfunc;
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} bx_uhci_core_t;
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#pragma pack (push, 1)
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struct TD {
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Bit32u dword0;
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Bit32u dword1;
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Bit32u dword2;
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Bit32u dword3;
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Bit32u resv[4];
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};
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#pragma pack (pop)
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#define HC_HORZ 0x80
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#define HC_VERT 0x81
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struct HCSTACK {
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Bit32u next;
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Bit8u d; // if queue, denotes VERT or HORZ
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bx_bool q;
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bx_bool t;
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};
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class bx_uhci_core_c : public bx_devmodel_c, public bx_pci_device_stub_c {
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public:
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bx_uhci_core_c();
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virtual ~bx_uhci_core_c();
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virtual void init_uhci(Bit8u devfunc, Bit16u devid, Bit8u headt, Bit8u intp);
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virtual void reset_uhci(unsigned);
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virtual void register_state(bx_list_c *parent);
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virtual void after_restore_state(void);
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virtual void set_port_device(int port, usb_device_c *dev);
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virtual void pci_write_handler(Bit8u address, Bit32u value, unsigned io_len);
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void event_handler(int event, USBPacket *packet, int port);
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protected:
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bx_uhci_core_t hub;
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Bit8u global_reset;
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bx_bool busy;
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USBAsync *packets;
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void update_irq(void);
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int broadcast_packet(USBPacket *p);
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void set_connect_status(Bit8u port, int type, bx_bool connected);
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static void uhci_timer_handler(void *);
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void uhci_timer(void);
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bx_bool DoTransfer(Bit32u address, Bit32u queue_num, struct TD *);
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void set_status(struct TD *td, bx_bool stalled, bx_bool data_buffer_error, bx_bool babble,
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bx_bool nak, bx_bool crc_time_out, bx_bool bitstuff_error, Bit16u act_len);
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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Bit32u read(Bit32u address, unsigned io_len);
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void write(Bit32u address, Bit32u value, unsigned io_len);
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};
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#endif
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