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Bochs/bochs/cpu/shift64.cc
Bryce Denney 0a7cb3a43c - apply patch.ifdef-disabled-options. Comments from that patch are below: 
For a whole lot of configure options, I put #if...#endif around code that
  is specific to the option, even in files which are normally only compiled
  when the option is on.  This allows me to create a MS Visual C++ 6.0
  workspace that supports many of these options.  The workspace will basically
  compile every file all the time, but the code for disabled options will
  be commented out by the #if...#endif.

  This may one day lead to simplification of the Makefiles and configure
  scripts, but for the moment I'm leaving Makefiles and configure scripts
  alone.

  Affected options:
    BX_SUPPORT_APIC (cpu/apic.cc)
    BX_SUPPORT_X86_64 (cpu/*64.cc)
    BX_DEBUGGER (debug/*)
    BX_DISASM (disasm/*)
    BX_WITH_nameofgui (gui/*)
    BX_SUPPORT_CDROM (iodev/cdrom.cc)
    BX_NE2K_SUPPORT (iodev/eth*.cc, iodev/ne2k.cc)
    BX_SUPPORT_APIC (iodev/ioapic.cc)
    BX_IODEBUG_SUPPORT (iodev/iodebug.cc)
    BX_PCI_SUPPORT (iodev/pci*.cc)
    BX_SUPPORT_SB16 (iodev/sb*.cc)

Modified Files:
  cpu/apic.cc cpu/arith64.cc cpu/ctrl_xfer64.cc
  cpu/data_xfer64.cc cpu/fetchdecode64.cc cpu/logical64.cc
  cpu/mult64.cc cpu/resolve64.cc cpu/shift64.cc cpu/stack64.cc
  debug/Makefile.in debug/crc.cc debug/dbg_main.cc debug/lexer.l
  debug/linux.cc debug/parser.c debug/parser.y
  disasm/dis_decode.cc disasm/dis_groups.cc gui/amigaos.cc
  gui/beos.cc gui/carbon.cc gui/macintosh.cc gui/rfb.cc
  gui/sdl.cc gui/term.cc gui/win32.cc gui/wx.cc gui/wxdialog.cc
  gui/wxmain.cc gui/x.cc iodev/cdrom.cc iodev/eth.cc
  iodev/eth_arpback.cc iodev/eth_fbsd.cc iodev/eth_linux.cc
  iodev/eth_null.cc iodev/eth_packetmaker.cc iodev/eth_tap.cc
  iodev/eth_tuntap.cc iodev/eth_win32.cc iodev/ioapic.cc
  iodev/iodebug.cc iodev/ne2k.cc iodev/pci.cc iodev/pci2isa.cc
  iodev/sb16.cc iodev/soundlnx.cc iodev/soundwin.cc
2002-11-19 05:47:45 +00:00

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/////////////////////////////////////////////////////////////////////////
// $Id: shift64.cc,v 1.9 2002-11-19 05:47:43 bdenney Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_X86_64
void
BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, result_64;
unsigned count;
/* op1:op2 << count. result stored in op1 */
if (i->b1() == 0x1a4)
count = i->Ib() & 0x3f;
else // 0x1a5
count = CL & 0x3f;
if (!count) return; /* NOP */
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
op2_64 = BX_READ_64BIT_REG(i->nnn());
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* SHLD count affects the following flags: S,Z,P,C,O
*/
set_CF((op1_64 >> (64 - count)) & 0x01);
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
set_ZF(result_64 == 0);
set_PF_base(result_64);
set_SF(result_64 >> 63);
}
void
BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("shrd_evgvib: not supported on < 386"));
#else
Bit64u op1_64, op2_64, result_64;
unsigned count;
if (i->b1() == 0x1ac)
count = i->Ib() & 0x3f;
else // 0x1ad
count = CL & 0x3f;
if (!count) return; /* NOP */
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
op2_64 = BX_READ_64BIT_REG(i->nnn());
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* SHRD count affects the following flags: S,Z,P,C,O
*/
set_CF((op1_64 >> (count - 1)) & 0x01);
set_ZF(result_64 == 0);
set_SF(result_64 >> 63);
/* for shift of 1, OF set if sign change occurred. */
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
set_PF_base(result_64);
#endif /* BX_CPU_LEVEL >= 3 */
}
void
BX_CPU_C::ROL_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (count) {
result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* ROL count affects the following flags: C
*/
set_CF(result_64 & 0x01);
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
}
}
void
BX_CPU_C::ROR_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64, result_b63;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (count) {
result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* ROR count affects the following flags: C
*/
result_b63 = result_64 & BX_CONST64(0x8000000000000000);
set_CF(result_b63 != 0);
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
}
}
void
BX_CPU_C::RCL_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (!count) return;
if (count==1) {
result_64 = (op1_64 << 1) | getB_CF();
}
else {
result_64 = (op1_64 << count) |
(getB_CF() << (count - 1)) |
(op1_64 >> (65 - count));
}
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* RCL count affects the following flags: C
*/
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
set_CF((op1_64 >> (64 - count)) & 0x01);
}
void
BX_CPU_C::RCR_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (!count) return;
if (count==1) {
result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
}
else {
result_64 = (op1_64 >> count) |
(getB_CF() << (64 - count)) |
(op1_64 << (65 - count));
}
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* RCR count affects the following flags: C
*/
set_CF((op1_64 >> (count - 1)) & 0x01);
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
}
void
BX_CPU_C::SHL_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (!count) return;
result_64 = (op1_64 << count);
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHL64);
}
void
BX_CPU_C::SHR_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (!count) return;
result_64 = (op1_64 >> count);
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
SET_FLAGS_OSZAPC_64(op1_64, count, result_64, BX_INSTR_SHR64);
}
void
BX_CPU_C::SAR_Eq(bxInstruction_c *i)
{
Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
count = i->Ib() & 0x3f;
else if (i->b1() == 0xd1)
count = 1;
else // (i->b1() == 0xd3)
count = CL & 0x3f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
if (!count) return;
/* count < 64, since only lower 5 bits used */
if (op1_64 & BX_CONST64(0x8000000000000000)) {
result_64 = (op1_64 >> count) | (BX_CONST64(0xffffffffffffffff) << (64 - count));
}
else {
result_64 = (op1_64 >> count);
}
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), result_64);
}
else {
Write_RMW_virtual_qword(result_64);
}
/* set eflags:
* SAR count affects the following flags: S,Z,P,C
*/
set_CF((op1_64 >> (count - 1)) & 0x01);
set_ZF(result_64 == 0);
set_SF(result_64 >> 63);
if (count == 1)
set_OF(0);
set_PF_base(result_64);
}
#endif /* if BX_SUPPORT_X86_64 */
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