291 lines
6.5 KiB
C++
291 lines
6.5 KiB
C++
// Copyright (C) 2000 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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void
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BX_CPU_C::MUL_AXEw(BxInstruction_t *i)
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{
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Bit16u op1_16, op2_16, product_16h, product_16l;
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Bit32u product_32;
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Boolean temp_flag;
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op1_16 = AX;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, &op2_16);
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}
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product_32 = ((Bit32u) op1_16) * ((Bit32u) op2_16);
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product_16l = (product_32 & 0xFFFF);
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product_16h = product_32 >> 16;
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/* now write product back to destination */
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AX = product_16l;
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DX = product_16h;
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/* set eflags:
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* MUL affects the following flags: C,O
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*/
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temp_flag = (product_16h != 0);
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SET_FLAGS_OxxxxC(temp_flag, temp_flag);
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}
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void
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BX_CPU_C::IMUL_AXEw(BxInstruction_t *i)
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{
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Bit16s op1_16, op2_16;
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Bit32s product_32;
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Bit16u product_16h, product_16l;
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op1_16 = AX;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, (Bit16u *) &op2_16);
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}
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product_32 = ((Bit32s) op1_16) * ((Bit32s) op2_16);
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product_16l = (product_32 & 0xFFFF);
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product_16h = product_32 >> 16;
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/* now write product back to destination */
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AX = product_16l;
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DX = product_16h;
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/* set eflags:
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* IMUL affects the following flags: C,O
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* IMUL r/m16: condition for clearing CF & OF:
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* DX:AX = sign-extend of AX
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*/
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if ( (DX==0xffff) && (AX & 0x8000) ) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else if ( (DX==0x0000) && (AX < 0x8000) ) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else {
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SET_FLAGS_OxxxxC(1, 1);
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}
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}
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void
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BX_CPU_C::DIV_AXEw(BxInstruction_t *i)
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{
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Bit16u op2_16, remainder_16, quotient_16l;
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Bit32u op1_32, quotient_32;
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op1_32 = (((Bit32u) DX) << 16) | ((Bit32u) AX);
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, &op2_16);
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}
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if (op2_16 == 0) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_32 = op1_32 / op2_16;
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remainder_16 = op1_32 % op2_16;
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quotient_16l = quotient_32 & 0xFFFF;
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if (quotient_32 != quotient_16l) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* DIV affects the following flags: O,S,Z,A,P,C are undefined
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*/
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#if INTEL_DIV_FLAG_BUG == 1
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set_CF(1);
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#endif
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/* now write quotient back to destination */
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AX = quotient_16l;
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DX = remainder_16;
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}
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void
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BX_CPU_C::IDIV_AXEw(BxInstruction_t *i)
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{
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Bit16s op2_16, remainder_16, quotient_16l;
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Bit32s op1_32, quotient_32;
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op1_32 = ((((Bit32u) DX) << 16) | ((Bit32u) AX));
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, (Bit16u *) &op2_16);
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}
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if (op2_16 == 0) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_32 = op1_32 / op2_16;
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remainder_16 = op1_32 % op2_16;
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quotient_16l = quotient_32 & 0xFFFF;
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if (quotient_32 != quotient_16l) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* IDIV affects the following flags: O,S,Z,A,P,C are undefined
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*/
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#if INTEL_DIV_FLAG_BUG == 1
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set_CF(1);
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#endif
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/* now write quotient back to destination */
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AX = quotient_16l;
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DX = remainder_16;
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}
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void
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BX_CPU_C::IMUL_GwEwIw(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 2
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bx_panic("IMUL_GvEvIv() unsupported on 8086!\n");
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#else
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Bit16u product_16l;
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Bit16s op2_16, op3_16;
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Bit32s product_32;
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op3_16 = i->Iw;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, (Bit16u *) &op2_16);
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}
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product_32 = op2_16 * op3_16;
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product_16l = (product_32 & 0xFFFF);
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/* now write product back to destination */
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BX_WRITE_16BIT_REG(i->nnn, product_16l);
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/* set eflags:
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* IMUL affects the following flags: C,O
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* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
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* result exactly fits within r16
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*/
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if (product_32 > -32768 && product_32 < 32767) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else {
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SET_FLAGS_OxxxxC(1, 1);
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}
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#endif
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}
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void
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BX_CPU_C::IMUL_GwEw(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 3
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bx_panic("IMUL_GvEv() unsupported on 8086!\n");
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#else
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Bit16u product_16l;
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Bit16s op1_16, op2_16;
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Bit32s product_32;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, (Bit16u *) &op2_16);
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}
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op1_16 = BX_READ_16BIT_REG(i->nnn);
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product_32 = op1_16 * op2_16;
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product_16l = (product_32 & 0xFFFF);
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/* now write product back to destination */
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BX_WRITE_16BIT_REG(i->nnn, product_16l);
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/* set eflags:
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* IMUL affects the following flags: C,O
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* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
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* result exactly fits within r16
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*/
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if (product_32 > -32768 && product_32 < 32767) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else {
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SET_FLAGS_OxxxxC(1, 1);
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}
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#endif
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}
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