439 lines
14 KiB
C++
439 lines
14 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: access.cc,v 1.112 2008-06-25 02:28:31 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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bx_bool BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned length)
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{
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Bit32u upper_limit;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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// Mark cache as being OK type for succeeding reads/writes
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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return 1;
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}
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#endif
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if (seg->cache.valid==0) {
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BX_DEBUG(("write_virtual_checks(): segment descriptor not valid"));
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return 0;
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}
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if (seg->cache.p == 0) { /* not present */
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BX_ERROR(("write_virtual_checks(): segment not present"));
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return 0;
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}
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switch (seg->cache.type) {
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case 0: case 1: // read only
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case 4: case 5: // read only, expand down
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case 8: case 9: // execute only
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case 10: case 11: // execute/read
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case 12: case 13: // execute only, conforming
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case 14: case 15: // execute/read-only, conforming
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BX_ERROR(("write_virtual_checks(): no write access to seg"));
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return 0;
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case 2: case 3: /* read/write */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled))
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{
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BX_ERROR(("write_virtual_checks(): write beyond limit, r/w"));
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return 0;
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding read/writes. The limit
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// checks still needs to be done though, but is more simple. We
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// could probably also optimize that out with a flag for the case
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// when limit is the maximum 32bit value. Limit should accomodate
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// at least a dword, since we subtract from it in the simple
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// limit check in other functions, and we don't want the value to roll.
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// Only normal segments (not expand down) are handled this way.
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seg->cache.valid |= SegAccessROK | SegAccessWOK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccessROK4G | SegAccessWOK4G;
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}
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break;
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case 6: case 7: /* read/write, expand down */
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if (seg->cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if ((offset <= seg->cache.u.segment.limit_scaled) ||
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(offset > upper_limit) || ((upper_limit - offset) < (length - 1)))
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{
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BX_ERROR(("write_virtual_checks(): write beyond limit, r/w ED"));
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return 0;
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}
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break;
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default:
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BX_PANIC(("write_virtual_checks(): unknown descriptor type=%d", seg->cache.type));
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}
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return 1;
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}
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bx_bool BX_CPP_AttrRegparmN(3)
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BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned length)
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{
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Bit32u upper_limit;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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// Mark cache as being OK type for succeeding reads/writes
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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return 1;
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}
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#endif
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if (seg->cache.valid==0) {
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BX_DEBUG(("read_virtual_checks(): segment descriptor not valid"));
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return 0;
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}
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if (seg->cache.p == 0) { /* not present */
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BX_ERROR(("read_virtual_checks(): segment not present"));
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return 0;
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}
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switch (seg->cache.type) {
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case 0: case 1: /* read only */
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case 2: case 3: /* read/write */
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case 10: case 11: /* execute/read */
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case 14: case 15: /* execute/read-only, conforming */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled))
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{
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BX_ERROR(("read_virtual_checks(): read beyond limit"));
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return 0;
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding reads. See notes for
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccessROK4G;
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}
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break;
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case 4: case 5: /* read only, expand down */
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case 6: case 7: /* read/write, expand down */
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if (seg->cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if ((offset <= seg->cache.u.segment.limit_scaled) ||
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(offset > upper_limit) || ((upper_limit - offset) < (length - 1)))
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{
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BX_ERROR(("read_virtual_checks(): read beyond limit ED"));
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return 0;
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}
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break;
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case 8: case 9: /* execute only */
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case 12: case 13: /* execute only, conforming */
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/* can't read or write an execute-only segment */
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BX_ERROR(("read_virtual_checks(): execute only"));
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return 0;
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default:
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BX_PANIC(("read_virtual_checks(): unknown descriptor type=%d", seg->cache.type));
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}
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return 1;
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}
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bx_bool BX_CPP_AttrRegparmN(3)
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BX_CPU_C::execute_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned length)
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{
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Bit32u upper_limit;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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// Mark cache as being OK type for succeeding reads/writes
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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return 1;
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}
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#endif
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if (seg->cache.valid==0) {
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BX_DEBUG(("execute_virtual_checks(): segment descriptor not valid"));
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return 0;
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}
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if (seg->cache.p == 0) { /* not present */
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BX_ERROR(("execute_virtual_checks(): segment not present"));
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return 0;
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}
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switch (seg->cache.type) {
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case 0: case 1: /* read only */
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case 2: case 3: /* read/write */
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case 10: case 11: /* execute/read */
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case 14: case 15: /* execute/read-only, conforming */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled))
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{
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BX_ERROR(("execute_virtual_checks(): read beyond limit"));
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return 0;
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding reads. See notes for
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccessROK4G;
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}
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break;
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case 8: case 9: /* execute only */
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case 12: case 13: /* execute only, conforming */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled))
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{
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BX_ERROR(("execute_virtual_checks(): read beyond limit execute only"));
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return 0;
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}
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break;
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case 4: case 5: /* read only, expand down */
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case 6: case 7: /* read/write, expand down */
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if (seg->cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if ((offset <= seg->cache.u.segment.limit_scaled) ||
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(offset > upper_limit) || ((upper_limit - offset) < (length - 1)))
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{
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BX_ERROR(("execute_virtual_checks(): read beyond limit ED"));
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return 0;
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}
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break;
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default:
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BX_PANIC(("execute_virtual_checks(): unknown descriptor type=%d", seg->cache.type));
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}
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return 1;
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}
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const char *BX_CPU_C::strseg(bx_segment_reg_t *seg)
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{
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES]) return("ES");
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else if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) return("CS");
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else if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS]) return("SS");
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else if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS]) return("DS");
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else if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS]) return("FS");
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else if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS]) return("GS");
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else {
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BX_PANIC(("undefined segment passed to strseg()!"));
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return("??");
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}
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}
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int BX_CPU_C::int_number(unsigned s)
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{
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if (s == BX_SEG_REG_SS)
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return BX_SS_EXCEPTION;
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else
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return BX_GP_EXCEPTION;
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}
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#if BX_SupportGuest2HostTLB
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Bit8u* BX_CPP_AttrRegparmN(2)
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BX_CPU_C::v2h_read_byte(bx_address laddr, unsigned curr_pl)
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{
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
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bx_address lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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if (tlbEntry->accessBits & (1<<curr_pl)) { // Read this pl OK.
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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return hostAddr;
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}
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}
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return 0;
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}
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Bit8u* BX_CPP_AttrRegparmN(2)
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BX_CPU_C::v2h_write_byte(bx_address laddr, unsigned curr_pl)
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{
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
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bx_address lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf)
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{
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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if (tlbEntry->accessBits & (0x10 << curr_pl)) {
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
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#endif
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return hostAddr;
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}
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}
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return 0;
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}
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Bit8u* BX_CPP_AttrRegparmN(3)
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BX_CPU_C::v2h_read(bx_address laddr, unsigned curr_pl, unsigned len)
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{
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// Make sure access does not span 2 pages.
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, len);
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bx_address lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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if (tlbEntry->accessBits & (1<<curr_pl)) { // Read this pl OK.
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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return hostAddr;
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}
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}
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return 0;
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}
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Bit8u* BX_CPP_AttrRegparmN(3)
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BX_CPU_C::v2h_write(bx_address laddr, unsigned curr_pl, unsigned len)
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{
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// Make sure access does not span 2 pages.
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, len);
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bx_address lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
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if (tlbEntry->lpf == lpf)
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{
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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if (tlbEntry->accessBits & (0x10 << curr_pl)) {
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bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
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Bit32u pageOffset = PAGE_OFFSET(laddr);
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Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(tlbEntry->ppf);
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#endif
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return hostAddr;
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}
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}
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return 0;
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}
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#endif // BX_SupportGuest2HostTLB
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//
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// Some macro defs to make things cleaner for endian-ness issues.
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// The following routines access a double qword, ie 16-bytes.
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// For the moment, I redirect these to use the single qword routines
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// by splitting one access into two.
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//
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// Endian Host byte order Guest (x86) byte order
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// ======================================================
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// Little 0..7 8..15 0..7 8..15
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// Big 15..8 7...0 0..7 8..15
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//
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// Below are the host memory offsets to each of 2 single quadwords, which
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// are different across big an little endian machines. The memory
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// accessing routines take care of the access endian issues when accessing
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// the physical memory image.
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//
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#ifdef BX_LITTLE_ENDIAN
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# define Host1stDWordOffset 0
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# define Host2ndDWordOffset 8
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#else
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# define Host1stDWordOffset 8
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# define Host2ndDWordOffset 0
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#endif
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::read_virtual_dqword(unsigned s, bx_address offset, Bit8u *data)
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{
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// Read Double Quadword.
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Bit64u *qwords = (Bit64u*) data;
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qwords[0] = read_virtual_qword(s, offset+Host1stDWordOffset);
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qwords[1] = read_virtual_qword(s, offset+Host2ndDWordOffset);
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::read_virtual_dqword_aligned(unsigned s, bx_address offset, Bit8u *data)
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{
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// If double quadword access is unaligned, #GP(0).
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bx_address laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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if (laddr & 0xf) {
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BX_DEBUG(("read_virtual_dqword_aligned(): access not aligned to 16-byte"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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read_virtual_dqword(s, offset, data);
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_dqword(unsigned s, bx_address offset, Bit8u *data)
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{
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// Write Double Quadword.
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Bit64u *qwords = (Bit64u*) data;
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write_virtual_qword(s, offset+Host1stDWordOffset, qwords[0]);
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write_virtual_qword(s, offset+Host2ndDWordOffset, qwords[1]);
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_virtual_dqword_aligned(unsigned s, bx_address offset, Bit8u *data)
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{
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// If double quadword access is unaligned, #GP(0).
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bx_address laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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if (laddr & 0xf) {
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BX_DEBUG(("write_virtual_dqword_aligned(): access not aligned to 16-byte"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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write_virtual_dqword(s, offset, data);
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}
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