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decoder.h
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define CPU feature's enum together with feature name in one place
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2023-10-15 23:56:11 +03:00 |
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disasm.cc
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fixed compilation of instrumentation examples with debugger OFF
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2023-04-06 22:18:01 +03:00 |
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features.h
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Implement support for LA57 and 5-level paging
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2023-12-29 14:48:38 +02:00 |
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fetchdecode32.cc
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fix compilation with minimalistic config
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2023-12-23 22:10:22 +02:00 |
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fetchdecode64.cc
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implemented MOVDIR64B instruction and enabled in TigerLake model
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2023-12-01 18:03:25 +02:00 |
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fetchdecode_avx.h
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coding style, cleanups and optimizations
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2023-11-19 20:31:05 +02:00 |
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fetchdecode_evex.h
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handle getexp methods though templates
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2023-12-25 08:07:07 +02:00 |
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fetchdecode_opmap_0f3a.h
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fixed compilation for VMX=1 X86_64=1
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2023-11-28 10:36:56 +02:00 |
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fetchdecode_opmap_0f38.h
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implemented MOVDIR64B instruction and enabled in TigerLake model
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2023-12-01 18:03:25 +02:00 |
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fetchdecode_opmap.h
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implement RDMSRLIST/WRMSRLIST instructions (+related VMX extensions) (#176)
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2023-12-16 21:59:34 +02:00 |
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fetchdecode_x87.h
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x87: Implemented special behavior for 287-compatibility FSTP opcode: D9D8..D9DF - Behaves the same as FSTP but won't cause a stack underflow exception.
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2023-12-07 12:56:02 +02:00 |
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fetchdecode_xop.h
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remove trailing whitespace from source files
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2022-08-23 21:46:04 +03:00 |
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fetchdecode.h
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style and disasm updates, no functional impact
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2023-12-25 14:57:05 +02:00 |
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ia_opcodes.def
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HandlersChaining Optimization: mark IN/OUT instructions as TraceEnd, they could have significant side effects like raising interrupts which have to be handled
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2024-01-05 08:45:10 +02:00 |
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ia_opcodes.h
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add into ia_opcodes.def disasm field for every instruction
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2020-03-28 14:23:54 +00:00 |
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instr.h
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fixed compilation of instrumentation examples with debugger OFF
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2023-04-06 22:18:01 +03:00 |
