569 lines
14 KiB
C++
569 lines
14 KiB
C++
/*
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*Emulator of an Intel 8254/82C54 Programmable Interval Timer.
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*
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*Things I am unclear on:
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*1.)What happens if both the status and count registers are latched,
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* but the first of the two count registers has already been read?
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* I.E.:
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* latch count 0 (16-bit)
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* Read count 0 (read LSByte)
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* READ_BACK status of count 0
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* Read count 0 - do you get MSByte or status?
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* This will be flagged as an error.
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*2.)What happens when we latch the output in the middle of a 2-part
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* unlatched read?
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*3.)I assumed that programming a counter removes a latched status.
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*4.)I implemented the 8254 description of mode 0, not the 82C54 one.
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*5.)clock() calls represent a rising clock edge followed by a falling
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* clock edge.
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*6.)What happens when we trigger mode 1 in the middle of a 2-part
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* write?
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*/
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#include "bochs.h"
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#define LOG_THIS this->
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class pit_82C54 : public logfunctions {
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private:
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enum {
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MAX_COUNTER=2,
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MAX_ADDRESS=3,
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CONTROL_ADDRESS=3,
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MAX_MODE=5
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};
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enum rw_status {
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LSByte=0,
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MSByte=1,
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LSByte_multiple=2,
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MSByte_multiple=3
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};
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enum real_RW_status {
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LSB_real=1,
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MSB_real=2,
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BOTH_real=3
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};
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struct counter_type {
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//Chip IOs;
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bool GATE; //GATE Input value at end of cycle
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bool OUT; //OUT output this cycle
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//Architected state;
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Bit32u count; //Counter value this cycle
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Bit16u outlatch; //Output latch this cycle
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Bit16u inlatch; //Input latch this cycle
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Bit8u status_latch;
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//Status Register data;
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Bit8u rw_mode; //2-bit R/W mode from command word register.
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Bit8u mode; //3-bit mode from command word register.
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bool bcd_mode; //1-bit BCD vs. Binary setting.
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bool null_count; //Null count bit of status register.
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//Latch status data;
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bool count_LSB_latched;
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bool count_MSB_latched;
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bool status_latched;
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//Miscelaneous State;
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bool triggerGATE; //Whether we saw GATE rise this cycle.
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rw_status write_state; //Read state this cycle
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rw_status read_state; //Read state this cycle
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bool count_written; //Whether a count written since programmed
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bool first_pass; //Whether or not this is the first loaded count.
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bool state_bit_1; //Miscelaneous state bits.
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bool state_bit_2;
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};
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counter_type counter[3];
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Bit8u controlword;
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void latch_counter(counter_type & thisctr) {
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if(thisctr.count_LSB_latched || thisctr.count_MSB_latched) {
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//Do nothing because previous latch has not been read.;
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} else {
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switch(thisctr.read_state) {
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case MSByte:
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thisctr.outlatch=thisctr.count & 0xFFFF;
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thisctr.count_MSB_latched=1;
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case LSByte:
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thisctr.outlatch=thisctr.count & 0xFFFF;
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thisctr.count_LSB_latched=1;
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case LSByte_multiple:
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thisctr.outlatch=thisctr.count & 0xFFFF;
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thisctr.count_LSB_latched=1;
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thisctr.count_MSB_latched=1;
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case MSByte_multiple:
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BX_ERROR(("Unknown behavior when latching during 2-part read."));
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//I guess latching and resetting to LSB first makes sense;
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thisctr.read_state=LSByte_multiple;
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thisctr.outlatch=thisctr.count & 0xFFFF;
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thisctr.count_LSB_latched=1;
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thisctr.count_MSB_latched=1;
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break;
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default:
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BX_ERROR(("Unknown read mode found during latch command."));
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break;
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}
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}
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}
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void set_OUT (counter_type & thisctr, bool data) {
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//This will probably have a callback, so I put it here.
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thisctr.OUT=data;
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}
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void decrement (counter_type & thisctr) {
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if(thisctr.bcd_mode) {
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if(!thisctr.count) {
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thisctr.count=0x9999;
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} else {
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int d0=thisctr.count & 0xF;
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int d1=(thisctr.count>>4)&0xF;
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int d2=(thisctr.count>>8)&0xF;
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int d3=(thisctr.count>>12)&0xF;
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if(d0) {
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d0--;
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} else {
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d0=0x9;
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if(d1) {
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d1--;
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} else {
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d1=0x9;
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if(d2) {
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d2--;
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} else {
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d2=0x9;
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d3--; //if d3==0, we would use the above zero case.;
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}
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}
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}
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}
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} else {
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if(!thisctr.count) {
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thisctr.count=0xFFFF;
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} else {
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thisctr.count--;
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}
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}
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}
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public:
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pit_82C54 (void) {
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Bit8u i;
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for(i=0;i<3;i++) {
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counter[i].read_state=LSByte;
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counter[i].write_state=LSByte;
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counter[i].GATE=1;
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counter[i].OUT=1;
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counter[i].triggerGATE=0;
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counter[i].mode=4;
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counter[i].first_pass=0;
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counter[i].bcd_mode=0;
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counter[i].count=0;
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counter[i].state_bit_1=0;
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counter[i].state_bit_2=0;
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counter[i].null_count=0;
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counter[i].rw_mode=1;
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counter[i].count_written=1;
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counter[i].count_LSB_latched=0;
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counter[i].count_MSB_latched=0;
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counter[i].status_latched=0;
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}
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}
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void clock(Bit8u cnum) {
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if(cnum>MAX_COUNTER) {
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BX_ERROR(("Counter number too high in clock");
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} else {
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counter_type & thisctr = counter[cnum];
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switch(thisctr.mode) {
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case 0:
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if(thisctr.count_written) {
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if(thisctr.null_count) {
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thisctr.count=thisctr.inlatch;
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thisctr.null_count=0;
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} else {
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if(thisctr.GATE && (thisctr.write_state!=MSByte_multiple)) {
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decrement(thisctr);
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if((!thisctr.count) && (!thisctr.OUT)) {
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set_OUT(thisctr,1);
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}
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}
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}
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}
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thisctr.triggerGATE=0;
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break;
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case 1:
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if(thisctr.count_written) {
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if(thisctr.triggerGATE) {
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thisctr.count=thisctr.inlatch;
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thisctr.null_count=0;
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set_OUT(thisctr,0);
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if(thisctr.write_state==MSByte_multiple) {
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BX_ERROR(("Undefined behavior when loading a half loaded count.")));
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}
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} else {
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decrement(thisctr);
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if((thisctr.count==0) && (!thisctr.OUT)) {
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set_OUT(thisctr,1);
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}
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}
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}
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thisctr.triggerGATE=0;
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break;
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case 2:
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if(thisctr.count_written) {
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if(thisctr.triggerGATE || thisctr.first_pass) {
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thisctr.count=thisctr.inlatch;
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thisctr.null_count=0;
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if(thisctr.inlatch==1) {
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BX_ERROR(("ERROR: count of 1 is invalid in pit mode 2.");
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}
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if(!thisctr.OUT) {
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set_OUT(thisctr,1);
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}
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if(thisctr.write_state==MSByte_multiple) {
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BX_ERROR(("Undefined behavior when loading a half loaded count.")));
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}
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thisctr.first_pass=0;
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} else {
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if(thisctr.GATE) {
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decrement(thisctr);
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if(thisctr.count==1) {
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set_OUT(thisctr,0);
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thisctr.first_pass=1;
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}
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}
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}
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}
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thisctr.triggerGATE=0;
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break;
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case 3:
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if(thisctr.count_written) {
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if( (thisctr.triggerGATE || thisctr.first_pass
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|| thisctr.state_bit_2) && thisctr.GATE ) {
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thisctr.count=thisctr.inlatch & 0xFFFE;
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thisctr.state_bit_1=thisctr.inlatch & 0x1;
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thisctr.null_count=0;
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if(thisctr.inlatch==1) {
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BX_ERROR(("Count of 1 is invalid in pit mode 3."));
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}
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if(!thisctr.OUT) {
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set_OUT(thisctr,1);
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} else if(thisctr.OUT && !thisctr.first_pass) {
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set_OUT(thisctr,0);
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}
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if(thisctr.write_state==MSByte_multiple) {
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BX_ERROR(("Undefined behavior when loading a half loaded count."));
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}
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thisctr.state_bit_2=0;
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thisctr.first_pass=0;
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} else {
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if(thisctr.GATE) {
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decrement(thisctr);
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decrement(thisctr);
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if(thisctr.count==0) {
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thisctr.state_bit_2=1;
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}
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if( (thisctr.count==2) &&
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( (!thisctr.OUT) || (!(thisctr.state_bit_1)))
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) {
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thisctr.state_bit_2=1;
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}
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}
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}
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}
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thisctr.triggerGATE=0;
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break;
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case 4:
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if(thisctr.count_written) {
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if(!thisctr.OUT) {
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set_OUT(thisctr,1);
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}
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if(thisctr.null_count) {
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thisctr.count=thisctr.inlatch;
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thisctr.null_count=0;
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if(thisctr.write_state==MSByte_multiple) {
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BX_ERROR(("Undefined behavior when loading a half loaded count."));
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}
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thisctr.first_pass=1;
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} else {
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if(thisctr.GATE) {
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decrement(thisctr);
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if( (!thisctr.count) && thisctr.first_pass) {
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set_OUT(thisctr,0);
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thisctr.first_pass=0;
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}
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}
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}
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}
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thisctr.triggerGATE=0;
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break;
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case 5:
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if(thisctr.count_written) {
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if(!thisctr.OUT) {
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set_OUT(thisctr,1);
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}
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if(thisctr.triggerGATE) {
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thisctr.count=thisctr.inlatch;
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thisctr.null_count=0;
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if(thisctr.write_state==MSByte_multiple) {
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BX_ERROR(("Undefined behavior when loading a half loaded count."));
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}
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thisctr.first_pass=1;
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} else {
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if(thisctr.GATE) {
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decrement(thisctr);
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if( (!thisctr.count) && thisctr.first_pass) {
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set_OUT(thisctr,0);
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thisctr.first_pass=0;
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}
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}
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}
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}
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thisctr.triggerGATE=0;
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break;
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default:
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BX_ERROR(("Mode not implemented."));
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thisctr.triggerGATE=0;
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break;
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}
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}
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}
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void clock_all(void) {
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clock(0);
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clock(1);
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clock(2);
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}
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Bit8u read(Bit8u address) {
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if(address>MAX_ADDRESS) {
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BX_ERROR(("Counter address incorrect in data read."));
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} else if(address==CONTROL_ADDRESS) {
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//Read from control word register;
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/* This might be okay. If so, 0 seems the most logical
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* return value from looking at the docs.
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*/
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BX_ERROR(("Read from control word register not defined."));
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return 0;
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} else {
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//Read from a counter;
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counter_type & thisctr=counter[address];
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if(thisctr.status_latched) {
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//Latched Status Read;
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if(thisctr.count_MSB_latched &&
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(thisctr.read_state==MSByte_multiple) ) {
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BX_ERROR(("Undefined output when status latched and count half read."));
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} else {
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thisctr.status_latched=0;
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return thisctr.status_latch;
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}
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} else {
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//Latched Count Read;
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if(thisctr.count_LSB_latched) {
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//Read Least Significant Byte;
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if(thisctr.read_state==LSByte_multiple) {
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thisctr.read_state=MSByte_multiple;
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}
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thisctr.count_LSB_latched=0;
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return (thisctr.outlatch & 0xFF);
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} else if(thisctr.count_MSB_latched) {
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//Read Most Significant Byte;
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if(thisctr.read_state==MSByte_multiple) {
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thisctr.read_state=LSByte_multiple;
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}
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thisctr.count_MSB_latched=0;
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return ((thisctr.outlatch>>8) & 0xFF);
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} else {
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//Unlatched Count Read;
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if(!(thisctr.read_state & 0x1)) {
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//Read Least Significant Byte;
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if(thisctr.read_state==LSByte_multiple) {
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thisctr.read_state=MSByte_multiple;
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}
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return (thisctr.count & 0xFF);
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} else {
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//Read Most Significant Byte;
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if(thisctr.read_state==MSByte_multiple) {
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thisctr.read_state=LSByte_multiple;
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}
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return ((thisctr.count>>8) & 0xFF);
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}
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}
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}
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}
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//Should only get here on errors;
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return 0;
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}
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void write(Bit8u address, Bit8u data) {
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if(address>MAX_ADDRESS) {
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BX_ERROR(("Counter address incorrect in data write."));
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} else if(address==CONTROL_ADDRESS) {
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Bit8u SC, RW, M, BCD;
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controlword=data;
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SC = (controlword>>6) & 0x3;
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RW = (controlword>>4) & 0x3;
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M = (controlword>>1) & 0x7;
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BCD = controlword & 0x1;
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if(SC == 3) {
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//READ_BACK command;
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int i;
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for(i=0;i<=MAX_COUNTER;i++) {
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if((M>>i) & 0x1) {
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//If we are using this counter;
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counter_type & thisctr=counter[i];
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if(!((controlword>>5) & 1)) {
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//Latch Count;
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latch_counter(thisctr);
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}
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if(!((controlword>>4) & 1)) {
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//Latch Status;
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if(thisctr.status_latched) {
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//Do nothing because latched status has not been read.;
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} else {
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thisctr.status_latch=
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((thisctr.OUT & 0x1) << 7) |
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((thisctr.null_count & 0x1) << 6) |
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((thisctr.rw_mode & 0x3) << 4) |
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((thisctr.mode & 0x7) << 1) |
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(thisctr.bcd_mode&0x1)
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;
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thisctr.status_latched=1;
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}
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}
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}
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}
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} else {
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counter_type & thisctr = counter[SC];
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if(!RW) {
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//Counter Latch command;
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latch_counter(thisctr);
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} else {
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//Counter Program Command;
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thisctr.null_count=1;
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thisctr.count_LSB_latched=0;
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thisctr.count_MSB_latched=0;
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thisctr.status_latched=0;
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thisctr.inlatch=0;
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thisctr.count_written=0;
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thisctr.first_pass=1;
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thisctr.rw_mode=RW;
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thisctr.bcd_mode=BCD;
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thisctr.mode=M;
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switch(RW) {
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case 0x1:
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thisctr.read_state=LSByte;
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thisctr.write_state=LSByte;
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break;
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case 0x2:
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thisctr.read_state=MSByte;
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thisctr.write_state=MSByte;
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break;
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case 0x3:
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thisctr.read_state=LSByte_multiple;
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thisctr.write_state=LSByte_multiple;
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break;
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default:
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BX_ERROR(("RW field invalid in control word write."));
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break;
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}
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//All modes except mode 0 have initial output of 1.;
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if(M) {
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set_OUT(thisctr, 1);
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} else {
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set_OUT(thisctr, 0);
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}
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}
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}
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} else {
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//Write to counter initial value.
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counter_type & thisctr = counter[address];
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switch(thisctr.write_state) {
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case LSByte_multiple:
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thisctr.inlatch=(thisctr.inlatch & (0xFF<<8)) | data;
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thisctr.write_state=MSByte_multiple;
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break;
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case LSByte:
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thisctr.inlatch=(thisctr.inlatch & (0xFF<<8)) | data;
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thisctr.null_count=1;
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thisctr.count_written=1;
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break;
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case MSByte_multiple:
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thisctr.write_state=LSByte_multiple;
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case MSByte: //shared between MSB_multiple and MSByte
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thisctr.inlatch=(thisctr.inlatch & 0xFF) | (data<<8);
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thisctr.null_count=1;
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thisctr.count_written=1;
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break;
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default:
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BX_ERROR(("write counter in invalid write state."));
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break;
|
|
}
|
|
switch(thisctr.mode) {
|
|
case 0:
|
|
if(thisctr.write_state==MSByte_multiple) {
|
|
set_OUT(thisctr,0);
|
|
}
|
|
break;
|
|
case 1:
|
|
break;
|
|
case 6:
|
|
case 2:
|
|
break;
|
|
case 7:
|
|
case 3:
|
|
break;
|
|
case 4:
|
|
break;
|
|
case 5:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void set_GATE(Bit8u cnum, bool data) {
|
|
if(cnum>MAX_COUNTER) {
|
|
BX_ERROR(("Counter number incorrect in 82C54 set_GATE"));
|
|
} else {
|
|
counter_type & thisctr = counter[cnum];
|
|
if((!thisctr.GATE)&&data) {
|
|
thisctr.triggerGATE=1;
|
|
}
|
|
thisctr.GATE=data;
|
|
switch(thisctr.mode) {
|
|
case 2:
|
|
if(!data) {
|
|
set_OUT(thisctr,1);
|
|
}
|
|
break;
|
|
case 3:
|
|
if(!data) {
|
|
set_OUT(thisctr,1);
|
|
thisctr.first_pass=1;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool read_OUT(Bit8u cnum) {
|
|
if(cnum>MAX_COUNTER) {
|
|
BX_ERROR(("Counter number incorrect in 82C54 read_OUT"));
|
|
return 0;
|
|
} else {
|
|
return counter[cnum].OUT;
|
|
}
|
|
}
|
|
|
|
};
|