206 lines
7.4 KiB
C++
206 lines
7.4 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2002-2009 Zwane Mwaikambo, Stanislav Shwartsman
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CPU_APIC_H
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#define BX_CPU_APIC_H 1
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#if BX_SUPPORT_APIC
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#define APIC_LEVEL_TRIGGERED 1
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#define APIC_EDGE_TRIGGERED 0
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#define BX_LAPIC_BASE_ADDR 0xfee00000 // default Local APIC address
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#define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
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#define BX_LAPIC_MAX_INTS 256
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#define BX_APIC_GLOBALLY_DISABLED 0
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#define BX_APIC_STATE_INVALID 1
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#define BX_APIC_XAPIC_MODE 2
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#define BX_APIC_X2APIC_MODE 3
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#define BX_XAPIC_EXT_SUPPORT_IER (1 << 0)
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#define BX_XAPIC_EXT_SUPPORT_SEOI (1 << 1)
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typedef Bit32u apic_dest_t; /* same definition in ioapic.h */
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class BOCHSAPI bx_local_apic_c : public logfunctions
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{
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bx_phy_address base_addr;
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unsigned mode;
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bx_bool xapic;
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#if BX_CPU_LEVEL >= 6
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Bit32u xapic_ext; // enabled extended XAPIC features
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#endif
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Bit32u apic_id; // 4 bit in legacy mode, 8 bit in XAPIC mode
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// 32 bit in X2APIC mode
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Bit32u apic_version_id;
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bx_bool software_enabled;
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Bit8u spurious_vector;
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bx_bool focus_disable;
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Bit32u task_priority; // Task priority (TPR)
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Bit32u ldr; // Logical destination (LDR)
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Bit32u dest_format; // Destination format (DFR)
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set.
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Bit8u isr[BX_LAPIC_MAX_INTS];
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// TMR=trigger mode register. Cleared for edge-triggered interrupts
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// and set for level-triggered interrupts. If set, local APIC must send
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// EOI message to all other APICs.
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Bit8u tmr[BX_LAPIC_MAX_INTS];
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// IRR=interrupt request register. When an interrupt is triggered by
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// the I/O APIC or another processor, it sets a bit in irr. The bit is
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LAPIC_MAX_INTS];
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#if BX_CPU_LEVEL >= 6
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// IER=interrupt enable register. Only vectors that are enabled in IER
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// participare in APIC's computation of highest priority pending interrupt.
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Bit8u ier[BX_LAPIC_MAX_INTS];
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#endif
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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#define APIC_ERR_RX_ILLEGAL_VEC 0x40
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#define APIC_ERR_TX_ILLEGAL_VEC 0x20
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#define X2APIC_ERR_REDIRECTIBLE_IPI 0x08
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#define APIC_ERR_RX_ACCEPT_ERR 0x08
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#define APIC_ERR_TX_ACCEPT_ERR 0x04
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#define APIC_ERR_RX_CHECKSUM 0x02
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#define APIC_ERR_TX_CHECKSUM 0x01
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// Error status Register (ESR)
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Bit32u error_status, shadow_error_status;
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Bit32u icr_hi; // Interrupt command register (ICR)
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Bit32u icr_lo;
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#define APIC_LVT_ENTRIES 6
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Bit32u lvt[APIC_LVT_ENTRIES];
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFMON 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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Bit32u timer_initial; // Initial timer count (in order to reload periodic timer)
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Bit32u timer_current; // Current timer count
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Bit64u ticksInitial; // Timer value when it started to count, also holds TSC-Deadline value
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Bit32u timer_divconf; // Timer divide configuration register
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Bit32u timer_divide_factor;
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// Internal timer state, not accessible from bus
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bx_bool timer_active;
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int timer_handle;
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_SMI 2
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/* RESERVED 3 */
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#define APIC_DM_NMI 4
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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#if BX_SUPPORT_VMX >= 2
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int vmx_timer_handle;
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Bit32u vmx_preemption_timer_value;
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Bit64u vmx_preemption_timer_initial; //The value of system tick when set the timer (absolute value)
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Bit64u vmx_preemption_timer_fire; //The value of system tick when fire the exception (absolute value)
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Bit32u vmx_preemption_timer_rate; //rate stated in MSR_VMX_MISC
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bx_bool vmx_timer_active;
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#endif
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BX_CPU_C *cpu;
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public:
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bx_bool INTR;
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bx_local_apic_c(BX_CPU_C *cpu, unsigned id);
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~bx_local_apic_c() { }
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void reset(unsigned type);
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bx_phy_address get_base(void) const { return base_addr; }
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void set_base(bx_phy_address newbase);
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Bit32u get_id() const { return apic_id; }
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bx_bool is_xapic() const { return xapic; }
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bx_bool is_selected(bx_phy_address addr);
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void read(bx_phy_address addr, void *data, unsigned len);
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void write(bx_phy_address addr, void *data, unsigned len);
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void write_aligned(bx_phy_address addr, Bit32u data);
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Bit32u read_aligned(bx_phy_address address);
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#if BX_CPU_LEVEL >= 6
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bx_bool read_x2apic(unsigned index, Bit64u *msr);
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bx_bool write_x2apic(unsigned index, Bit64u msr);
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#endif
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// on local APIC, trigger means raise the CPU's INTR line. For now
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// I also have to raise pc_system.INTR but that should be replaced
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// with the cpu-specific INTR signals.
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void trigger_irq(Bit8u vector, unsigned trigger_mode, bx_bool bypass_irr_isr = 0);
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void untrigger_irq(Bit8u vector, unsigned trigger_mode);
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Bit8u acknowledge_int(void); // only the local CPU should call this
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int highest_priority_int(Bit8u *array);
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void receive_EOI(Bit32u value);
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void send_ipi(apic_dest_t dest, Bit32u lo_cmd);
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void write_spurious_interrupt_register(Bit32u value);
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void service_local_apic(void);
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void print_status(void);
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bx_bool match_logical_addr(apic_dest_t address);
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bx_bool deliver(Bit8u vector, Bit8u delivery_mode, Bit8u trig_mode);
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Bit8u get_tpr(void) { return task_priority; }
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void set_tpr(Bit8u tpr);
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Bit8u get_ppr(void);
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Bit8u get_apr(void);
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bx_bool is_focus(Bit8u vector);
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void set_lvt_entry(unsigned apic_reg, Bit32u val);
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static void periodic_smf(void *);
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void periodic(void);
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void set_divide_configuration(Bit32u value);
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void set_initial_timer_count(Bit32u value);
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Bit32u get_current_timer_count(void);
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#if BX_CPU_LEVEL >= 6
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Bit64u get_tsc_deadline(void);
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void set_tsc_deadline(Bit64u value);
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void receive_SEOI(Bit8u vec);
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#endif
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void startup_msg(Bit8u vector);
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void register_state(bx_param_c *parent);
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#if BX_SUPPORT_VMX >= 2
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Bit32u read_vmx_preemption_timer(void);
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void set_vmx_preemption_timer(Bit32u value);
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void deactivate_vmx_preemption_timer(void);
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static void vmx_preemption_timer_expired(void *);
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#endif
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};
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int apic_bus_deliver_lowest_priority(Bit8u vector, apic_dest_t dest, bx_bool trig_mode, bx_bool broadcast);
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BOCHSAPI_MSVCONLY int apic_bus_deliver_interrupt(Bit8u vector, apic_dest_t dest, Bit8u delivery_mode, bx_bool logical_dest, bx_bool level, bx_bool trig_mode);
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int apic_bus_broadcast_interrupt(Bit8u vector, Bit8u delivery_mode, bx_bool trig_mode, int exclude_cpu);
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#endif // if BX_SUPPORT_APIC
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#endif
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