733 lines
22 KiB
C++
Executable File
733 lines
22 KiB
C++
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id: msr.cc,v 1.41 2010-03-15 15:48:01 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008-2009 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64==0
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// Make life easier for merging code.
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#define RAX EAX
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#define RDX EDX
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#endif
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#if BX_CPU_LEVEL >= 5
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bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
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{
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Bit64u val64 = 0;
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switch(index) {
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#if BX_CPU_LEVEL >= 6
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case BX_MSR_SYSENTER_CS:
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("RDMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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val64 = BX_CPU_THIS_PTR msr.sysenter_cs_msr;
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break;
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case BX_MSR_SYSENTER_ESP:
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("RDMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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val64 = BX_CPU_THIS_PTR msr.sysenter_esp_msr;
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break;
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case BX_MSR_SYSENTER_EIP:
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("RDMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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val64 = BX_CPU_THIS_PTR msr.sysenter_eip_msr;
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break;
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#endif
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#if BX_CPU_LEVEL >= 6
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case BX_MSR_MTRRCAP: // read only MSR
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val64 = BX_CONST64(0x0000000000000508);
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break;
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case BX_MSR_MTRRPHYSBASE0:
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case BX_MSR_MTRRPHYSMASK0:
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case BX_MSR_MTRRPHYSBASE1:
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case BX_MSR_MTRRPHYSMASK1:
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case BX_MSR_MTRRPHYSBASE2:
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case BX_MSR_MTRRPHYSMASK2:
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case BX_MSR_MTRRPHYSBASE3:
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case BX_MSR_MTRRPHYSMASK3:
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case BX_MSR_MTRRPHYSBASE4:
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case BX_MSR_MTRRPHYSMASK4:
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case BX_MSR_MTRRPHYSBASE5:
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case BX_MSR_MTRRPHYSMASK5:
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case BX_MSR_MTRRPHYSBASE6:
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case BX_MSR_MTRRPHYSMASK6:
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case BX_MSR_MTRRPHYSBASE7:
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case BX_MSR_MTRRPHYSMASK7:
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val64 = BX_CPU_THIS_PTR msr.mtrrphys[index - BX_MSR_MTRRPHYSBASE0];
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break;
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case BX_MSR_MTRRFIX64K_00000:
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val64 = BX_CPU_THIS_PTR msr.mtrrfix64k_00000;
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break;
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case BX_MSR_MTRRFIX16K_80000:
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case BX_MSR_MTRRFIX16K_A0000:
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val64 = BX_CPU_THIS_PTR msr.mtrrfix16k[index - BX_MSR_MTRRFIX16K_80000];
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break;
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case BX_MSR_MTRRFIX4K_C0000:
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case BX_MSR_MTRRFIX4K_C8000:
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case BX_MSR_MTRRFIX4K_D0000:
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case BX_MSR_MTRRFIX4K_D8000:
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case BX_MSR_MTRRFIX4K_E0000:
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case BX_MSR_MTRRFIX4K_E8000:
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case BX_MSR_MTRRFIX4K_F0000:
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case BX_MSR_MTRRFIX4K_F8000:
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val64 = BX_CPU_THIS_PTR msr.mtrrfix4k[index - BX_MSR_MTRRFIX4K_C0000];
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break;
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case BX_MSR_PAT:
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val64 = BX_CPU_THIS_PTR msr.pat;
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break;
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case BX_MSR_MTRR_DEFTYPE:
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val64 = BX_CPU_THIS_PTR msr.mtrr_deftype;
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break;
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#endif
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case BX_MSR_TSC:
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val64 = BX_CPU_THIS_PTR get_TSC();
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break;
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#if BX_SUPPORT_APIC
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case BX_MSR_APICBASE:
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val64 = BX_CPU_THIS_PTR msr.apicbase;
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BX_INFO(("RDMSR: Read %08x:%08x from MSR_APICBASE", GET32H(val64), GET32L(val64)));
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break;
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#endif
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#if BX_SUPPORT_VMX
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/*
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case BX_MSR_IA32_SMM_MONITOR_CTL:
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BX_PANIC(("Dual-monitor treatment of SMI and SMM is not implemented"));
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break;
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*/
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case BX_MSR_IA32_FEATURE_CONTROL:
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val64 = BX_CPU_THIS_PTR msr.ia32_feature_ctrl;
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break;
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case BX_MSR_VMX_BASIC:
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val64 = VMX_MSR_VMX_BASIC;
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break;
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case BX_MSR_VMX_PINBASED_CTRLS:
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val64 = VMX_MSR_VMX_PINBASED_CTRLS;
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break;
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case BX_MSR_VMX_PROCBASED_CTRLS:
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val64 = VMX_MSR_VMX_PROCBASED_CTRLS;
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break;
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case BX_MSR_VMX_VMEXIT_CTRLS:
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val64 = VMX_MSR_VMX_VMEXIT_CTRLS;
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break;
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case BX_MSR_VMX_VMENTRY_CTRLS:
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val64 = VMX_MSR_VMX_VMENTRY_CTRLS;
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break;
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case BX_MSR_VMX_PROCBASED_CTRLS2:
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val64 = VMX_MSR_VMX_PROCBASED_CTRLS2;
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break;
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case BX_MSR_VMX_MISC:
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val64 = VMX_MSR_MISC;
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break;
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case BX_MSR_VMX_CR0_FIXED0:
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val64 = VMX_MSR_CR0_FIXED0;
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break;
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case BX_MSR_VMX_CR0_FIXED1:
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val64 = VMX_MSR_CR0_FIXED1;
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break;
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case BX_MSR_VMX_CR4_FIXED0:
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val64 = VMX_MSR_CR4_FIXED0;
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break;
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case BX_MSR_VMX_CR4_FIXED1:
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val64 = VMX_MSR_CR4_FIXED1;
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break;
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case BX_MSR_VMX_VMCS_ENUM:
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val64 = VMX_MSR_VMCS_ENUM;
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break;
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#endif
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#if BX_SUPPORT_X86_64
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case BX_MSR_EFER:
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val64 = BX_CPU_THIS_PTR efer.get32();
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break;
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case BX_MSR_STAR:
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val64 = MSR_STAR;
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break;
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case BX_MSR_LSTAR:
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val64 = MSR_LSTAR;
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break;
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case BX_MSR_CSTAR:
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val64 = MSR_CSTAR;
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break;
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case BX_MSR_FMASK:
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val64 = MSR_FMASK;
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break;
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case BX_MSR_FSBASE:
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val64 = MSR_FSBASE;
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break;
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case BX_MSR_GSBASE:
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val64 = MSR_GSBASE;
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break;
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case BX_MSR_KERNELGSBASE:
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val64 = MSR_KERNELGSBASE;
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break;
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case BX_MSR_TSC_AUX:
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val64 = MSR_TSC_AUX; // 32 bit MSR
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break;
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#endif // #if BX_SUPPORT_X86_64
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default:
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#if BX_CONFIGURE_MSRS
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if (index < BX_MSR_MAX_INDEX && BX_CPU_THIS_PTR msrs[index]) {
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val64 = BX_CPU_THIS_PTR msrs[index]->get64();
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break;
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}
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#endif
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("RDMSR: Unknown register %#x", index));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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*msr = val64;
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return 1;
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}
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#endif // BX_CPU_LEVEL >= 5
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDMSR(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 5
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if (!real_mode() && CPL != 0) {
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BX_ERROR(("RDMSR: CPL != 0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u index = ECX;
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Bit64u val64 = 0;
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#if BX_SUPPORT_VMX
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VMexit_MSR(i, VMX_VMEXIT_RDMSR, index);
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#endif
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if (!rdmsr(index, &val64))
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exception(BX_GP_EXCEPTION, 0);
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RAX = GET32L(val64);
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RDX = GET32H(val64);
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#endif
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}
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#if BX_CPU_LEVEL >= 6
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BX_CPP_INLINE bx_bool isMemTypeValidMTRR(unsigned memtype)
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{
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switch(memtype) {
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case BX_MEMTYPE_UC:
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case BX_MEMTYPE_WC:
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case BX_MEMTYPE_WT:
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case BX_MEMTYPE_WP:
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case BX_MEMTYPE_WB:
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return 1;
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default:
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return 0;
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}
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}
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BX_CPP_INLINE bx_bool isMemTypeValidPAT(unsigned memtype)
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{
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return (memtype == 0x07) /* UC- */ || isMemTypeValidMTRR(memtype);
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}
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#endif
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#if BX_CPU_LEVEL >= 5
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bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
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{
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Bit32u val32_lo = GET32L(val_64);
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Bit32u val32_hi = GET32H(val_64);
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BX_INSTR_WRMSR(BX_CPU_ID, index, val_64);
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switch(index) {
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#if BX_CPU_LEVEL >= 6
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case BX_MSR_SYSENTER_CS:
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("WRMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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BX_CPU_THIS_PTR msr.sysenter_cs_msr = val32_lo;
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break;
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case BX_MSR_SYSENTER_ESP:
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("WRMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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#if BX_SUPPORT_X86_64
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if (! IsCanonical(val_64)) {
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BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_SYSENTER_ESP !"));
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return 0;
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}
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#endif
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BX_CPU_THIS_PTR msr.sysenter_esp_msr = val_64;
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break;
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case BX_MSR_SYSENTER_EIP:
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
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// failed to find the MSR, could #GP or ignore it silently
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BX_ERROR(("WRMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
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if (! BX_CPU_THIS_PTR ignore_bad_msrs)
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return 0; // will result in #GP fault due to unknown MSR
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}
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#if BX_SUPPORT_X86_64
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if (! IsCanonical(val_64)) {
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BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_SYSENTER_EIP !"));
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return 0;
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}
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#endif
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BX_CPU_THIS_PTR msr.sysenter_eip_msr = val_64;
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break;
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#endif
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#if BX_CPU_LEVEL >= 6
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case BX_MSR_MTRRCAP:
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BX_ERROR(("WRMSR: MTRRCAP is read only MSR"));
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return 0;
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case BX_MSR_MTRRPHYSBASE0:
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case BX_MSR_MTRRPHYSBASE1:
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case BX_MSR_MTRRPHYSBASE2:
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case BX_MSR_MTRRPHYSBASE3:
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case BX_MSR_MTRRPHYSBASE4:
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case BX_MSR_MTRRPHYSBASE5:
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case BX_MSR_MTRRPHYSBASE6:
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case BX_MSR_MTRRPHYSBASE7:
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if (! IsValidPhyAddr(val_64)) {
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BX_ERROR(("WRMSR[0x%08x]: attempt to write invalid phy addr to variable range MTRR %08x:%08x", index, val32_hi, val32_lo));
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return 0;
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}
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// handle 8-11 reserved bits
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if (! isMemTypeValidMTRR(val32_lo & 0xFFF)) {
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BX_ERROR(("WRMSR: attempt to write invalid Memory Type to BX_MSR_MTRRPHYSBASE"));
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return 0;
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}
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BX_CPU_THIS_PTR msr.mtrrphys[index - BX_MSR_MTRRPHYSBASE0] = val_64;
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break;
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case BX_MSR_MTRRPHYSMASK0:
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case BX_MSR_MTRRPHYSMASK1:
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case BX_MSR_MTRRPHYSMASK2:
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case BX_MSR_MTRRPHYSMASK3:
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case BX_MSR_MTRRPHYSMASK4:
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case BX_MSR_MTRRPHYSMASK5:
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case BX_MSR_MTRRPHYSMASK6:
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case BX_MSR_MTRRPHYSMASK7:
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if (! IsValidPhyAddr(val_64)) {
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BX_ERROR(("WRMSR[0x%08x]: attempt to write invalid phy addr to variable range MTRR %08x:%08x", index, val32_hi, val32_lo));
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return 0;
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}
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// handle 10-0 reserved bits
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if (val32_lo & 0x7ff) {
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BX_ERROR(("WRMSR[0x%08x]: variable range MTRR reserved bits violation %08x:%08x", index, val32_hi, val32_lo));
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return 0;
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}
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BX_CPU_THIS_PTR msr.mtrrphys[index - BX_MSR_MTRRPHYSBASE0] = val_64;
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break;
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case BX_MSR_MTRRFIX64K_00000:
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if (! isMemTypeValidMTRR(val32_lo & 0xFF) ||
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! isMemTypeValidMTRR((val32_lo >> 8) & 0xFF) ||
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! isMemTypeValidMTRR((val32_lo >> 16) & 0xFF) ||
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! isMemTypeValidMTRR(val32_lo >> 24) ||
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! isMemTypeValidMTRR(val32_hi & 0xFF) ||
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! isMemTypeValidMTRR((val32_hi >> 8) & 0xFF) ||
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! isMemTypeValidMTRR((val32_hi >> 16) & 0xFF) ||
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! isMemTypeValidMTRR(val32_hi >> 24))
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{
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BX_ERROR(("WRMSR: attempt to write invalid Memory Type to MSR_MTRRFIX64K_00000 !"));
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return 0;
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}
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BX_CPU_THIS_PTR msr.mtrrfix64k_00000 = val_64;
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break;
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case BX_MSR_MTRRFIX16K_80000:
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case BX_MSR_MTRRFIX16K_A0000:
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if (! isMemTypeValidMTRR(val32_lo & 0xFF) ||
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! isMemTypeValidMTRR((val32_lo >> 8) & 0xFF) ||
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! isMemTypeValidMTRR((val32_lo >> 16) & 0xFF) ||
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! isMemTypeValidMTRR(val32_lo >> 24) ||
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! isMemTypeValidMTRR(val32_hi & 0xFF) ||
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! isMemTypeValidMTRR((val32_hi >> 8) & 0xFF) ||
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! isMemTypeValidMTRR((val32_hi >> 16) & 0xFF) ||
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! isMemTypeValidMTRR(val32_hi >> 24))
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{
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BX_ERROR(("WRMSR: attempt to write invalid Memory Type to MSR_MTRRFIX16K regsiter !"));
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return 0;
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}
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BX_CPU_THIS_PTR msr.mtrrfix16k[index - BX_MSR_MTRRFIX16K_80000] = val_64;
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break;
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case BX_MSR_MTRRFIX4K_C0000:
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case BX_MSR_MTRRFIX4K_C8000:
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case BX_MSR_MTRRFIX4K_D0000:
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case BX_MSR_MTRRFIX4K_D8000:
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case BX_MSR_MTRRFIX4K_E0000:
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case BX_MSR_MTRRFIX4K_E8000:
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case BX_MSR_MTRRFIX4K_F0000:
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case BX_MSR_MTRRFIX4K_F8000:
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if (! isMemTypeValidMTRR(val32_lo & 0xFF) ||
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! isMemTypeValidMTRR((val32_lo >> 8) & 0xFF) ||
|
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! isMemTypeValidMTRR((val32_lo >> 16) & 0xFF) ||
|
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! isMemTypeValidMTRR(val32_lo >> 24) ||
|
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! isMemTypeValidMTRR(val32_hi & 0xFF) ||
|
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! isMemTypeValidMTRR((val32_hi >> 8) & 0xFF) ||
|
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! isMemTypeValidMTRR((val32_hi >> 16) & 0xFF) ||
|
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! isMemTypeValidMTRR(val32_hi >> 24))
|
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{
|
|
BX_ERROR(("WRMSR: attempt to write invalid Memory Type to fixed memory range MTRR !"));
|
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return 0;
|
|
}
|
|
BX_CPU_THIS_PTR msr.mtrrfix4k[index - BX_MSR_MTRRFIX4K_C0000] = val_64;
|
|
break;
|
|
|
|
case BX_MSR_PAT:
|
|
if (! isMemTypeValidPAT(val32_lo & 0xFF) ||
|
|
! isMemTypeValidPAT((val32_lo >> 8) & 0xFF) ||
|
|
! isMemTypeValidPAT((val32_lo >> 16) & 0xFF) ||
|
|
! isMemTypeValidPAT(val32_lo >> 24) ||
|
|
! isMemTypeValidPAT(val32_hi & 0xFF) ||
|
|
! isMemTypeValidPAT((val32_hi >> 8) & 0xFF) ||
|
|
! isMemTypeValidPAT((val32_hi >> 16) & 0xFF) ||
|
|
! isMemTypeValidPAT(val32_hi >> 24))
|
|
{
|
|
BX_ERROR(("WRMSR: attempt to write invalid Memory Type to MSR_PAT"));
|
|
return 0;
|
|
}
|
|
|
|
BX_CPU_THIS_PTR msr.pat = val_64;
|
|
break;
|
|
|
|
case BX_MSR_MTRR_DEFTYPE:
|
|
if (! isMemTypeValidMTRR(val32_lo & 0xFF)) {
|
|
BX_ERROR(("WRMSR: attempt to write invalid Memory Type to MSR_MTRR_DEFTYPE"));
|
|
return 0;
|
|
}
|
|
if (val32_hi || (val32_lo & 0xfffff300)) {
|
|
BX_ERROR(("WRMSR: attempt to reserved bits in MSR_MTRR_DEFTYPE"));
|
|
return 0;
|
|
}
|
|
BX_CPU_THIS_PTR msr.mtrr_deftype = val32_lo;
|
|
break;
|
|
#endif
|
|
|
|
case BX_MSR_TSC:
|
|
BX_INFO(("WRMSR: write 0x%08x%08x to MSR_TSC", val32_hi, val32_lo));
|
|
BX_CPU_THIS_PTR set_TSC(val_64);
|
|
break;
|
|
|
|
#if BX_SUPPORT_APIC
|
|
case BX_MSR_APICBASE:
|
|
return relocate_apic(val_64);
|
|
#endif
|
|
|
|
#if BX_SUPPORT_VMX
|
|
// Support only two bits: lock bit (bit 0) and VMX enable (bit 2)
|
|
case BX_MSR_IA32_FEATURE_CONTROL:
|
|
if (BX_CPU_THIS_PTR msr.ia32_feature_ctrl & 0x1) {
|
|
BX_ERROR(("WRMSR: IA32_FEATURE_CONTROL_MSR VMX lock bit is set !"));
|
|
return 0;
|
|
}
|
|
/*
|
|
if (val_64 & ~((Bit64u)(BX_IA32_FEATURE_CONTROL_BITS))) {
|
|
BX_ERROR(("WRMSR: attempt to set reserved bits of IA32_FEATURE_CONTROL_MSR !"));
|
|
return 0;
|
|
}
|
|
*/
|
|
BX_CPU_THIS_PTR msr.ia32_feature_ctrl = val32_lo;
|
|
break;
|
|
|
|
case BX_MSR_VMX_BASIC:
|
|
case BX_MSR_VMX_PINBASED_CTRLS:
|
|
case BX_MSR_VMX_PROCBASED_CTRLS:
|
|
case BX_MSR_VMX_VMEXIT_CTRLS:
|
|
case BX_MSR_VMX_VMENTRY_CTRLS:
|
|
case BX_MSR_VMX_MISC:
|
|
case BX_MSR_VMX_CR0_FIXED0:
|
|
case BX_MSR_VMX_CR0_FIXED1:
|
|
case BX_MSR_VMX_CR4_FIXED0:
|
|
case BX_MSR_VMX_CR4_FIXED1:
|
|
case BX_MSR_VMX_VMCS_ENUM:
|
|
case BX_MSR_VMX_TRUE_PINBASED_CTRLS:
|
|
case BX_MSR_VMX_TRUE_PROCBASED_CTRLS:
|
|
case BX_MSR_VMX_PROCBASED_CTRLS2:
|
|
case BX_MSR_VMX_TRUE_VMEXIT_CTRLS:
|
|
case BX_MSR_VMX_TRUE_VMENTRY_CTRLS:
|
|
BX_ERROR(("WRMSR: VMX read only MSR"));
|
|
return 0;
|
|
#endif
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
case BX_MSR_EFER:
|
|
if (val_64 & ~BX_EFER_SUPPORTED_BITS) {
|
|
BX_ERROR(("WRMSR: attempt to set reserved bits of EFER MSR !"));
|
|
return 0;
|
|
}
|
|
|
|
/* #GP(0) if changing EFER.LME when cr0.pg = 1 */
|
|
if ((BX_CPU_THIS_PTR efer.get_LME() != ((val32_lo >> 8) & 1)) &&
|
|
BX_CPU_THIS_PTR cr0.get_PG())
|
|
{
|
|
BX_ERROR(("WRMSR: attempt to change LME when CR0.PG=1"));
|
|
return 0;
|
|
}
|
|
|
|
BX_CPU_THIS_PTR efer.set32((val32_lo & BX_EFER_SUPPORTED_BITS & ~BX_EFER_LMA_MASK)
|
|
| (BX_CPU_THIS_PTR efer.get32() & BX_EFER_LMA_MASK)); // keep LMA untouched
|
|
break;
|
|
|
|
case BX_MSR_STAR:
|
|
MSR_STAR = val_64;
|
|
break;
|
|
|
|
case BX_MSR_LSTAR:
|
|
if (! IsCanonical(val_64)) {
|
|
BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_LSTAR !"));
|
|
return 0;
|
|
}
|
|
MSR_LSTAR = val_64;
|
|
break;
|
|
|
|
case BX_MSR_CSTAR:
|
|
if (! IsCanonical(val_64)) {
|
|
BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_CSTAR !"));
|
|
return 0;
|
|
}
|
|
MSR_CSTAR = val_64;
|
|
break;
|
|
|
|
case BX_MSR_FMASK:
|
|
MSR_FMASK = (Bit32u) val_64;
|
|
break;
|
|
|
|
case BX_MSR_FSBASE:
|
|
if (! IsCanonical(val_64)) {
|
|
BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_FSBASE !"));
|
|
return 0;
|
|
}
|
|
MSR_FSBASE = val_64;
|
|
break;
|
|
|
|
case BX_MSR_GSBASE:
|
|
if (! IsCanonical(val_64)) {
|
|
BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_GSBASE !"));
|
|
return 0;
|
|
}
|
|
MSR_GSBASE = val_64;
|
|
break;
|
|
|
|
case BX_MSR_KERNELGSBASE:
|
|
if (! IsCanonical(val_64)) {
|
|
BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_KERNELGSBASE !"));
|
|
return 0;
|
|
}
|
|
MSR_KERNELGSBASE = val_64;
|
|
break;
|
|
|
|
case BX_MSR_TSC_AUX:
|
|
MSR_TSC_AUX = val32_lo;
|
|
break;
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
|
|
default:
|
|
#if BX_CONFIGURE_MSRS
|
|
if (index < BX_MSR_MAX_INDEX && BX_CPU_THIS_PTR msrs[index]) {
|
|
if (! BX_CPU_THIS_PTR msrs[index]->set64(val_64)) {
|
|
BX_ERROR(("WRMSR: Write failed to MSR %#x - #GP fault", index));
|
|
return 0;
|
|
}
|
|
break;
|
|
}
|
|
#endif
|
|
// failed to find the MSR, could #GP or ignore it silently
|
|
BX_ERROR(("WRMSR: Unknown register %#x", index));
|
|
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
|
return 0; // will result in #GP fault due to unknown MSR
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
#endif // BX_CPU_LEVEL >= 5
|
|
|
|
#if BX_SUPPORT_APIC
|
|
bx_bool BX_CPU_C::relocate_apic(Bit64u val_64)
|
|
{
|
|
/* MSR_APICBASE
|
|
* [0:7] Reserved
|
|
* [8] This is set if CPU is BSP
|
|
* [9] Reserved
|
|
* [10] X2APIC mode bit (1=enabled 0=disabled)
|
|
* [11] APIC Global Enable bit (1=enabled 0=disabled)
|
|
* [12:M] APIC Base Address (physical)
|
|
* [M:63] Reserved
|
|
*/
|
|
|
|
#define BX_MSR_APICBASE_RESERVED_BITS 0x6ff
|
|
|
|
if (BX_CPU_THIS_PTR msr.apicbase & 0x800) {
|
|
Bit32u val32_hi = GET32H(val_64), val32_lo = GET32L(val_64);
|
|
BX_INFO(("WRMSR: wrote %08x:%08x to MSR_APICBASE", val32_hi, val32_lo));
|
|
#if BX_SUPPORT_X86_64
|
|
if (! IsValidPhyAddr(val_64)) {
|
|
BX_ERROR(("relocate_apic: invalid physical address"));
|
|
return 0;
|
|
}
|
|
#endif
|
|
if (val32_lo & BX_MSR_APICBASE_RESERVED_BITS) {
|
|
BX_ERROR(("relocate_apic: attempt to set reserved bits"));
|
|
return 0;
|
|
}
|
|
BX_CPU_THIS_PTR msr.apicbase = (bx_phy_address) val_64;
|
|
BX_CPU_THIS_PTR lapic.set_base(BX_CPU_THIS_PTR msr.apicbase);
|
|
// TLB flush is required for emulation correctness
|
|
TLB_flush(); // don't care about performance of apic relocation
|
|
|
|
if ((val32_lo & 0x800) == 0) {
|
|
// APIC global enable bit cleared, clear APIC on chip CPUID feature flag
|
|
BX_CPU_THIS_PTR cpuid_std_function[0x1].edx &= ~(1<<9);
|
|
BX_CPU_THIS_PTR cpuid_ext_function[0x1].edx &= ~(1<<9);
|
|
}
|
|
}
|
|
else {
|
|
BX_INFO(("WRMSR: MSR_APICBASE APIC global enable bit cleared !"));
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::WRMSR(bxInstruction_c *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 5
|
|
if (!real_mode() && CPL != 0) {
|
|
BX_ERROR(("WRMSR: CPL != 0 not in real mode"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
Bit64u val_64 = ((Bit64u) EDX << 32) | EAX;
|
|
Bit32u index = ECX;
|
|
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_MSR(i, VMX_VMEXIT_WRMSR, index);
|
|
#endif
|
|
|
|
if (! wrmsr(index, val_64))
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
#endif
|
|
}
|
|
|
|
#if BX_CONFIGURE_MSRS
|
|
|
|
int BX_CPU_C::load_MSRs(const char *file)
|
|
{
|
|
char line[512];
|
|
unsigned linenum = 0;
|
|
Bit32u index, type;
|
|
Bit32u reset_hi, reset_lo;
|
|
Bit32u rsrv_hi, rsrv_lo;
|
|
Bit32u ignr_hi, ignr_lo;
|
|
|
|
FILE *fd = fopen (file, "r");
|
|
if (fd == NULL) return -1;
|
|
int retval = 0;
|
|
do {
|
|
linenum++;
|
|
char* ret = fgets(line, sizeof(line)-1, fd);
|
|
line[sizeof(line) - 1] = '\0';
|
|
size_t len = strlen(line);
|
|
if (len>0 && line[len-1] < ' ')
|
|
line[len-1] = '\0';
|
|
|
|
if (ret != NULL && strlen(line)) {
|
|
if (line[0] == '#') continue;
|
|
retval = sscanf(line, "%x %d %08x %08x %08x %08x %08x %08x",
|
|
&index, &type, &reset_hi, &reset_lo, &rsrv_hi, &rsrv_lo, &ignr_hi, &ignr_lo);
|
|
|
|
if (retval < 8) {
|
|
retval = -1;
|
|
BX_PANIC(("%s:%d > error parsing MSRs config file!", file, linenum));
|
|
break; // quit parsing after first error
|
|
}
|
|
if (index >= BX_MSR_MAX_INDEX) {
|
|
BX_PANIC(("%s:%d > MSR index is too big !", file, linenum));
|
|
continue;
|
|
}
|
|
if (BX_CPU_THIS_PTR msrs[index]) {
|
|
BX_PANIC(("%s:%d > MSR[0x%03x] is already defined!", file, linenum, index));
|
|
continue;
|
|
}
|
|
if (type > 2) {
|
|
BX_PANIC(("%s:%d > MSR[0x%03x] unknown type !", file, linenum, index));
|
|
continue;
|
|
}
|
|
|
|
BX_INFO(("loaded MSR[0x%03x] type=%d %08x:%08x %08x:%08x %08x:%08x", index, type,
|
|
reset_hi, reset_lo, rsrv_hi, rsrv_lo, ignr_hi, ignr_lo));
|
|
|
|
BX_CPU_THIS_PTR msrs[index] = new MSR(index, type,
|
|
((Bit64u)(reset_hi) << 32) | reset_lo,
|
|
((Bit64u) (rsrv_hi) << 32) | rsrv_lo,
|
|
((Bit64u) (ignr_hi) << 32) | ignr_lo);
|
|
}
|
|
} while (!feof(fd));
|
|
|
|
fclose(fd);
|
|
return retval;
|
|
}
|
|
|
|
#endif
|