ab6b9c7dcb
* Fully supports * MMX/XMM/3DNOW instruction sets * FPU instruction * SSE3 extensions currently only 16/32 bit mode bug anyway, it is much better that old one ;)
312 lines
8.9 KiB
C++
312 lines
8.9 KiB
C++
#ifndef _BX_DISASM_H_
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#define _BX_DISASM_H_
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#include "config.h"
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#define BX_DECODE_MODRM(modrm_byte, mod, opcode, rm) { \
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mod = (modrm_byte >> 6) & 0x03; \
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opcode = (modrm_byte >> 3) & 0x07; \
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rm = modrm_byte & 0x07; \
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}
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#define BX_DECODE_SIB(sib_byte, scale, index, base) { \
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scale = sib >> 6; \
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index = (sib >> 3) & 0x07; \
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base = sib & 0x07; \
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}
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// to be used in future
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#define IF_8086 0x00000000 /* 8086 instruction */
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#define IF_186 0x00000000 /* 186+ instruction */
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#define IF_286 0x00000000 /* 286+ instruction */
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#define IF_386 0x00000000 /* 386+ instruction */
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#define IF_387 0x00000000 /* 387+ FPU instruction */
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#define IF_486 0x00000000 /* 486+ instruction */
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#define IF_PENTIUM 0x00000000 /* Pentium instruction */
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#define IF_P6 0x00000000 /* P6 instruction */
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#define IF_KATMAI 0x00000000 /* Katmai instruction */
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#define IF_WILLAMETTE 0x00000000 /* Willamette instruction */
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#define IF_PRESCOTT 0x00000000 /* Prescott instruction */
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#define IF_ARITHMETIC 0x00000000 /* arithmetic instruction */
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#define IF_LOGIC 0x00000000 /* logic instruction */
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#define IF_SYSTEM 0x00000000 /* system instruction (require CPL=0) */
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#define IF_FPU 0x00000000 /* FPU instruction */
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#define IF_MMX 0x00000000 /* MMX instruction */
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#define IF_3DNOW 0x00000000 /* 3DNow! instruction */
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#define IF_KNI 0x00000000 /* Katmai new instruction */
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#define IF_PREFETCH 0x00000000 /* Prefetch instruction */
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#define IF_SSE 0x00000000 /* SSE instruction */
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#define IF_SSE2 0x00000000 /* SSE2 instruction */
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#define IF_PNI 0x00000000 /* Prescott new instruction */
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enum {
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AL_REG,
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CL_REG,
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DL_REG,
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BL_REG,
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AH_REG,
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CH_REG,
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DH_REG,
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BH_REG
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};
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enum {
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AX_REG,
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CX_REG,
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DX_REG,
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BX_REG,
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SP_REG,
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BP_REG,
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SI_REG,
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DI_REG
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};
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enum {
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eAX_REG,
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eCX_REG,
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eDX_REG,
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eBX_REG,
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eSP_REG,
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eBP_REG,
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eSI_REG,
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eDI_REG
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};
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enum {
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ES_REG,
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CS_REG,
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SS_REG,
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DS_REG,
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FS_REG,
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GS_REG
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};
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#define X_MODE 0x0
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#define B_MODE 0x1
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#define W_MODE 0x2
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#define D_MODE 0x3
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#define V_MODE 0x4
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#define Q_MODE 0x5
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#define O_MODE 0x6
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#define T_MODE 0x7
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#define P_MODE 0x8
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class disassembler;
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typedef void (disassembler::*BxDisasmPtr_t) (unsigned attr);
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typedef void (disassembler::*BxDisasmResolveModrmPtr_t) (unsigned attr);
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class disassembler {
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public:
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disassembler() {}
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unsigned disasm(bx_bool is_32, Bit32u base, Bit32u ip, Bit8u *instr, char *disbuf);
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private:
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bx_bool i32bit_opsize;
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bx_bool i32bit_addrsize;
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Bit8u modrm, mod, nnn, rm;
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Bit8u sib, scale, index, base;
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union {
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Bit8u displ8;
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Bit16u displ16;
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Bit32u displ32;
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} displacement;
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Bit32u db_eip;
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Bit32u db_base;
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unsigned n_prefixes;
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Bit8u *instruction_begin; // keep track of where instruction starts
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Bit8u *instruction; // for fetching of next byte of instruction
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const char *seg_override;
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char *disbufptr;
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BxDisasmResolveModrmPtr_t resolve_modrm;
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BX_CPP_INLINE Bit8u fetch_byte() {
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db_eip++;
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return(*instruction++);
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};
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BX_CPP_INLINE Bit8u peek_byte() {
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return(*instruction);
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};
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BX_CPP_INLINE Bit16u fetch_word() {
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Bit8u b0 = * (Bit8u *) instruction++;
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Bit8u b1 = * (Bit8u *) instruction++;
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Bit16u ret16 = (b1<<8) | b0;
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db_eip += 2;
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return(ret16);
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};
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BX_CPP_INLINE Bit32u fetch_dword() {
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Bit8u b0 = * (Bit8u *) instruction++;
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Bit8u b1 = * (Bit8u *) instruction++;
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Bit8u b2 = * (Bit8u *) instruction++;
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Bit8u b3 = * (Bit8u *) instruction++;
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Bit32u ret32 = (b3<<24) | (b2<<16) | (b1<<8) | b0;
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db_eip += 4;
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return(ret32);
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};
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void dis_sprintf(char *fmt, ...);
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void decode_modrm();
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public:
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/*
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* Codes for Addressing Method:
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* ---------------------------
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* A - Direct address. The instruction has no ModR/M byte; the address
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* of the operand is encoded in the instruction; and no base register,
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* index register, or scaling factor can be applied.
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* C - The reg field of the ModR/M byte selects a control register.
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* D - The reg field of the ModR/M byte selects a debug register.
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* E - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either a general-purpose register or a memory address.
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* If it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, a displacement.
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* F - EFLAGS Register.
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* G - The reg field of the ModR/M byte selects a general register.
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* I - Immediate data. The operand value is encoded in subsequent bytes of
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* the instruction.
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* J - The instruction contains a relative offset to be added to the
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* instruction pointer register.
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* M - The ModR/M byte may refer only to memory.
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* O - The instruction has no ModR/M byte; the offset of the operand is
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* coded as a word or double word (depending on address size attribute)
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* in the instruction. No base register, index register, or scaling
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* factor can be applied.
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* P - The reg field of the ModR/M byte selects a packed quadword MMX
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* technology register.
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* Q - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either an MMX technology register or a memory address.
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* If it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, and a displacement.
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* R - The mod field of the ModR/M byte may refer only to a general register.
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* S - The reg field of the ModR/M byte selects a segment register.
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* T - The reg field of the ModR/M byte selects a test register.
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* V - The reg field of the ModR/M byte selects a 128-bit XMM register.
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* W - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either a 128-bit XMM register or a memory address. If
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* it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, and a displacement.
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* X - Memory addressed by the DS:SI register pair.
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* Y - Memory addressed by the ES:DI register pair.
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*/
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/*
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* Codes for Operand Type:
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* ----------------------
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* a - Two one-word operands in memory or two double-word operands in
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* memory, depending on operand-size attribute (used only by the BOUND
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* instruction).
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* b - Byte, regardless of operand-size attribute.
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* d - Doubleword, regardless of operand-size attribute.
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* dq - Double-quadword, regardless of operand-size attribute.
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* p - 32-bit or 48-bit pointer, depending on operand-size attribute.
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* pi - Quadword MMX technology register (e.g. mm0)
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* ps - 128-bit packed single-precision floating-point data.
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* q - Quadword, regardless of operand-size attribute.
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* s - 6-byte pseudo-descriptor.
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* ss - Scalar element of a 128-bit packed single-precision floating data.
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* si - Doubleword integer register (e.g., eax)
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* v - Word or doubleword, depending on operand-size attribute.
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* w - Word, regardless of operand-size attribute.
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*/
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void XX (unsigned) {}
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// fpu
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void ST0 (unsigned) { dis_sprintf("st(0)"); }
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void STj (unsigned);
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// general/segment register
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void Rd (unsigned);
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void Rw (unsigned);
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void Sw (unsigned);
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// control/debug register
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void Cd (unsigned) { dis_sprintf("cr%d", nnn); }
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void Dd (unsigned) { dis_sprintf("db%d", nnn); }
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void Td (unsigned) { dis_sprintf("tr%d", nnn); }
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// segment register (implicit)
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void OP_SEG (unsigned);
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// general purpose register
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void reg8 (unsigned);
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void reg16 (unsigned);
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void reg32 (unsigned);
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// memory only
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void OP_MEM (unsigned);
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void OP_X (unsigned);
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void OP_Y (unsigned);
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// mmx/xmm
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void OP_P (unsigned);
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void OP_Q (unsigned);
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void OP_W (unsigned);
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void OP_V (unsigned);
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// immediate
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void I1 (unsigned) { dis_sprintf("1"); }
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void Ib (unsigned);
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void Iw (unsigned);
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void Id (unsigned);
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void Iv (unsigned);
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void sIb (unsigned);
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void Eb (unsigned);
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void Ew (unsigned);
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void Ed (unsigned);
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void Ev (unsigned);
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void Ea (unsigned);
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void Ep (unsigned);
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void Gb (unsigned);
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void Gw (unsigned);
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void Gv (unsigned);
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void Gd (unsigned);
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void Ap (unsigned);
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void Ob (unsigned);
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void Ov (unsigned);
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// jump
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void Jb (unsigned);
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void Jv (unsigned);
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private:
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void resolve16_mod0 (unsigned mode);
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void resolve16_mod1 (unsigned mode);
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void resolve16_mod2 (unsigned mode);
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void resolve32_mod0 (unsigned mode);
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void resolve32_mod1 (unsigned mode);
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void resolve32_mod2 (unsigned mode);
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void resolve32_mod0_rm4 (unsigned mode);
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void resolve32_mod1_rm4 (unsigned mode);
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void resolve32_mod2_rm4 (unsigned mode);
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void print_datasize (unsigned mode);
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};
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#endif
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