870 lines
27 KiB
C++
870 lines
27 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2021 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "cpu/cpu.h"
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#include "gui/siminterface.h"
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#include "param_names.h"
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#include "tigerlake.h"
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#define LOG_THIS cpu->
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#if BX_SUPPORT_X86_64 && BX_SUPPORT_AVX
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#define VMCS_REVISION_ID 0x04
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tigerlake_t::tigerlake_t(BX_CPU_C *cpu):
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#if BX_SUPPORT_VMX
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bx_cpuid_t(cpu, VMCS_REVISION_ID)
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#else
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bx_cpuid_t(cpu)
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#endif
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{
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if (! BX_SUPPORT_X86_64)
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BX_PANIC(("You must enable x86-64 for Intel Core i7 Icelake configuration"));
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enable_cpu_extension(BX_ISA_X87);
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enable_cpu_extension(BX_ISA_486);
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enable_cpu_extension(BX_ISA_PENTIUM);
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enable_cpu_extension(BX_ISA_P6);
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enable_cpu_extension(BX_ISA_MMX);
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enable_cpu_extension(BX_ISA_SYSENTER_SYSEXIT);
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enable_cpu_extension(BX_ISA_CLFLUSH);
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enable_cpu_extension(BX_ISA_DEBUG_EXTENSIONS);
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enable_cpu_extension(BX_ISA_VME);
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enable_cpu_extension(BX_ISA_PSE);
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enable_cpu_extension(BX_ISA_PAE);
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enable_cpu_extension(BX_ISA_PGE);
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#if BX_PHY_ADDRESS_LONG
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enable_cpu_extension(BX_ISA_PSE36);
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#endif
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enable_cpu_extension(BX_ISA_MTRR);
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enable_cpu_extension(BX_ISA_PAT);
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enable_cpu_extension(BX_ISA_XAPIC);
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enable_cpu_extension(BX_ISA_X2APIC);
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enable_cpu_extension(BX_ISA_LONG_MODE);
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enable_cpu_extension(BX_ISA_LM_LAHF_SAHF);
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enable_cpu_extension(BX_ISA_CMPXCHG16B);
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enable_cpu_extension(BX_ISA_NX);
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enable_cpu_extension(BX_ISA_1G_PAGES);
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enable_cpu_extension(BX_ISA_PCID);
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enable_cpu_extension(BX_ISA_TSC_ADJUST);
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enable_cpu_extension(BX_ISA_TSC_DEADLINE);
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enable_cpu_extension(BX_ISA_SSE);
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enable_cpu_extension(BX_ISA_SSE2);
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enable_cpu_extension(BX_ISA_SSE3);
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enable_cpu_extension(BX_ISA_SSSE3);
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enable_cpu_extension(BX_ISA_SSE4_1);
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enable_cpu_extension(BX_ISA_SSE4_2);
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enable_cpu_extension(BX_ISA_POPCNT);
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#if BX_SUPPORT_MONITOR_MWAIT
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enable_cpu_extension(BX_ISA_MONITOR_MWAIT);
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#endif
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#if BX_SUPPORT_VMX >= 2
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enable_cpu_extension(BX_ISA_VMX);
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#endif
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enable_cpu_extension(BX_ISA_RDTSCP);
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enable_cpu_extension(BX_ISA_XSAVE);
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enable_cpu_extension(BX_ISA_XSAVEOPT);
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enable_cpu_extension(BX_ISA_AES_PCLMULQDQ);
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enable_cpu_extension(BX_ISA_MOVBE);
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enable_cpu_extension(BX_ISA_AVX);
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enable_cpu_extension(BX_ISA_AVX_F16C);
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enable_cpu_extension(BX_ISA_AVX2);
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enable_cpu_extension(BX_ISA_AVX_FMA);
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enable_cpu_extension(BX_ISA_LZCNT);
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enable_cpu_extension(BX_ISA_BMI1);
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enable_cpu_extension(BX_ISA_BMI2);
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enable_cpu_extension(BX_ISA_ADX);
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enable_cpu_extension(BX_ISA_FSGSBASE);
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enable_cpu_extension(BX_ISA_INVPCID);
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enable_cpu_extension(BX_ISA_SMEP);
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enable_cpu_extension(BX_ISA_SMAP);
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enable_cpu_extension(BX_ISA_RDRAND);
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enable_cpu_extension(BX_ISA_RDSEED);
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enable_cpu_extension(BX_ISA_FDP_DEPRECATION);
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enable_cpu_extension(BX_ISA_FCS_FDS_DEPRECATION);
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enable_cpu_extension(BX_ISA_SHA);
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#if BX_SUPPORT_EVEX
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enable_cpu_extension(BX_ISA_GFNI);
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enable_cpu_extension(BX_ISA_VAES_VPCLMULQDQ);
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enable_cpu_extension(BX_ISA_AVX512);
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enable_cpu_extension(BX_ISA_AVX512_VL);
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enable_cpu_extension(BX_ISA_AVX512_DQ);
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enable_cpu_extension(BX_ISA_AVX512_CD);
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enable_cpu_extension(BX_ISA_AVX512_BW);
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enable_cpu_extension(BX_ISA_AVX512_IFMA52);
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enable_cpu_extension(BX_ISA_AVX512_VBMI);
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enable_cpu_extension(BX_ISA_AVX512_VBMI2);
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enable_cpu_extension(BX_ISA_AVX512_VNNI);
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enable_cpu_extension(BX_ISA_AVX512_BITALG);
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enable_cpu_extension(BX_ISA_AVX512_VPOPCNTDQ);
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enable_cpu_extension(BX_ISA_AVX512_VP2INTERSECT);
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#endif
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enable_cpu_extension(BX_ISA_CLFLUSHOPT);
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enable_cpu_extension(BX_ISA_CLWB);
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enable_cpu_extension(BX_ISA_XSAVEC);
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enable_cpu_extension(BX_ISA_XSAVES);
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#if BX_SUPPORT_PKEYS
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enable_cpu_extension(BX_ISA_PKU);
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#endif
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#if BX_SUPPORT_CET
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enable_cpu_extension(BX_ISA_CET);
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#endif
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enable_cpu_extension(BX_ISA_UMIP);
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enable_cpu_extension(BX_ISA_RDPID);
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enable_cpu_extension(BX_ISA_SCA_MITIGATIONS);
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}
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void tigerlake_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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{
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static const char* brand_string = "11th Gen Intel(R) Core(TM) i5-1135G7 @ 2.40GHz";
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static bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
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if (cpuid_limit_winnt)
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if (function > 2 && function < 0x80000000) function = 2;
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switch(function) {
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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get_ext_cpuid_brand_string_leaf(brand_string, function, leaf);
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return;
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case 0x80000005:
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get_reserved_leaf(leaf);
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return;
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case 0x80000006:
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get_ext_cpuid_leaf_6(leaf);
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return;
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case 0x80000007:
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get_ext_cpuid_leaf_7(leaf);
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return;
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case 0x80000008:
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get_ext_cpuid_leaf_8(leaf);
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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case 0x00000002:
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get_std_cpuid_leaf_2(leaf);
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return;
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case 0x00000003:
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get_reserved_leaf(leaf);
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return;
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case 0x00000004:
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get_std_cpuid_leaf_4(subfunction, leaf);
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return;
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case 0x00000005:
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get_std_cpuid_leaf_5(leaf);
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return;
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case 0x00000006:
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get_std_cpuid_leaf_6(leaf);
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return;
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case 0x00000007:
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get_std_cpuid_leaf_7(subfunction, leaf);
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return;
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case 0x00000008:
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case 0x00000009:
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get_reserved_leaf(leaf);
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return;
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case 0x0000000A:
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get_std_cpuid_leaf_A(leaf);
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return;
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case 0x0000000B:
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get_std_cpuid_extended_topology_leaf(subfunction, leaf);
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return;
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case 0x0000000C:
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get_reserved_leaf(leaf);
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return;
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case 0x0000000D:
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get_std_cpuid_xsave_leaf(subfunction, leaf);
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return;
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case 0x0000000E:
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case 0x0000000F:
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case 0x00000010:
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case 0x00000011:
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case 0x00000012: // SGX Capability
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case 0x00000013:
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case 0x00000014: // Processor Trace
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get_reserved_leaf(leaf);
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return;
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case 0x00000015:
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get_std_cpuid_leaf_15(leaf);
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return;
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case 0x00000016:
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get_std_cpuid_leaf_16(leaf);
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return;
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case 0x00000017:
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get_reserved_leaf(leaf);
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return;
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case 0x00000018:
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get_std_cpuid_leaf_18(subfunction, leaf);
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return;
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case 0x00000019:
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case 0x0000001A:
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case 0x0000001B: // PCONFIG Information
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default:
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get_reserved_leaf(leaf);
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return;
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}
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}
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#if BX_SUPPORT_VMX >= 2
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Bit32u tigerlake_t::get_vmx_extensions_bitmask(void) const
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{
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return BX_VMX_TPR_SHADOW |
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BX_VMX_VIRTUAL_NMI |
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BX_VMX_APIC_VIRTUALIZATION |
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BX_VMX_WBINVD_VMEXIT |
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BX_VMX_MONITOR_TRAP_FLAG |
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BX_VMX_VPID |
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BX_VMX_EPT |
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BX_VMX_UNRESTRICTED_GUEST |
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BX_VMX_SAVE_DEBUGCTL_DISABLE |
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BX_VMX_PERF_GLOBAL_CTRL |
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BX_VMX_PAT |
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BX_VMX_EFER |
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BX_VMX_DESCRIPTOR_TABLE_EXIT |
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BX_VMX_X2APIC_VIRTUALIZATION |
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BX_VMX_PREEMPTION_TIMER |
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BX_VMX_PAUSE_LOOP_EXITING |
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BX_VMX_EPT_ACCESS_DIRTY |
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BX_VMX_VINTR_DELIVERY |
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BX_VMX_VMCS_SHADOWING |
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BX_VMX_EPTP_SWITCHING |
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BX_VMX_EPT_EXCEPTION |
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BX_VMX_PML |
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BX_VMX_SW_INTERRUPT_INJECTION_ILEN_0 |
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/* BX_VMX_POSTED_INSTERRUPTS - not implemented yet */
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/* BX_VMX_MBE_CONTROL - not implemeted yet */
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BX_VMX_SPP |
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BX_VMX_TSC_SCALING;
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}
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#endif
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// leaf 0x00000000 //
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void tigerlake_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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// EAX: highest std function understood by CPUID
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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get_leaf_0(0x1B, "GenuineIntel", leaf);
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}
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// leaf 0x00000001 //
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void tigerlake_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x000806c1;
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// EBX:
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// [7:0] Brand ID
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// [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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unsigned n_logical_processors = ncores*nthreads;
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leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8) |
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(n_logical_processors << 16);
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#if BX_SUPPORT_APIC
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leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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// * [0:0] SSE3: SSE3 Instructions
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// * [1:1] PCLMULQDQ Instruction support
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// * [2:2] DTES64: 64-bit DS area
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// * [3:3] MONITOR/MWAIT support
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// * [4:4] DS-CPL: CPL qualified debug store
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// * [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// * [7:7] EST: Enhanced Intel SpeedStep Technology
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// * [8:8] TM2: Thermal Monitor 2
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// * [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// * [12:12] FMA Instructions support
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// * [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// * [14:14] xTPR update control
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// * [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// * [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// * [19:19] SSE4.1 Instructions
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// * [20:20] SSE4.2 Instructions
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// * [21:21] X2APIC
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// * [22:22] MOVBE instruction
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// * [23:23] POPCNT instruction
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// * [24:24] TSC Deadline
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// * [25:25] AES Instructions
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// * [26:26] XSAVE extensions support
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// * [27:27] OSXSAVE support
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// * [28:28] AVX extensions support
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// * [29:29] AVX F16C - Float16 conversion support
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// * [30:30] RDRAND instruction
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// [31:31] reserved
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leaf->ecx = BX_CPUID_EXT_SSE3 |
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BX_CPUID_EXT_PCLMULQDQ |
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BX_CPUID_EXT_DTES64 |
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#if BX_SUPPORT_MONITOR_MWAIT
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BX_CPUID_EXT_MONITOR_MWAIT |
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#endif
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BX_CPUID_EXT_DS_CPL |
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#if BX_SUPPORT_VMX >= 2
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BX_CPUID_EXT_VMX |
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#endif
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BX_CPUID_EXT_EST |
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BX_CPUID_EXT_THERMAL_MONITOR2 |
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BX_CPUID_EXT_SSSE3 |
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BX_CPUID_EXT_FMA |
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BX_CPUID_EXT_CMPXCHG16B |
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BX_CPUID_EXT_xTPR |
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BX_CPUID_EXT_PDCM |
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BX_CPUID_EXT_PCID |
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BX_CPUID_EXT_SSE4_1 |
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BX_CPUID_EXT_SSE4_2 |
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BX_CPUID_EXT_X2APIC |
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BX_CPUID_EXT_MOVBE |
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BX_CPUID_EXT_POPCNT |
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BX_CPUID_EXT_TSC_DEADLINE |
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BX_CPUID_EXT_AES |
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BX_CPUID_EXT_XSAVE |
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BX_CPUID_EXT_AVX |
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BX_CPUID_EXT_AVX_F16C |
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BX_CPUID_EXT_RDRAND;
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if (cpu->cr4.get_OSXSAVE())
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leaf->ecx |= BX_CPUID_EXT_OSXSAVE;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSENTER/SYSEXIT support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// * [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// * [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// * [21:21] DS: Debug Store
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// * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] SSE: SSE Extensions
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// * [26:26] SSE2: SSE2 Extensions
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// * [27:27] Self Snoop
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// * [28:28] Hyper Threading Technology
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// * [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// * [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD_SYSENTER_SYSEXIT |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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BX_CPUID_STD_PSE36 |
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BX_CPUID_STD_CLFLUSH |
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BX_CPUID_STD_DEBUG_STORE |
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BX_CPUID_STD_ACPI |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD_SSE |
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BX_CPUID_STD_SSE2 |
|
|
BX_CPUID_STD_SELF_SNOOP |
|
|
#if BX_SUPPORT_SMP
|
|
BX_CPUID_STD_HT |
|
|
#endif
|
|
BX_CPUID_STD_THERMAL_MONITOR |
|
|
BX_CPUID_STD_PBE;
|
|
#if BX_SUPPORT_APIC
|
|
// if MSR_APICBASE APIC Global Enable bit has been cleared,
|
|
// the CPUID feature flag for the APIC is set to 0.
|
|
if (cpu->msr.apicbase & 0x800)
|
|
leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
|
|
#endif
|
|
}
|
|
|
|
// leaf 0x00000002 //
|
|
void tigerlake_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x00000002 - Cache and TLB Descriptors
|
|
leaf->eax = 0x00feff01;
|
|
leaf->ebx = 0x000000f0;
|
|
leaf->ecx = 0x00000000;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x00000003 - Processor Serial Number (not supported) //
|
|
|
|
// leaf 0x00000004 //
|
|
void tigerlake_t::get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x00000004 - Deterministic Cache Parameters
|
|
switch(subfunction) {
|
|
case 0:
|
|
leaf->eax = 0x1c004121;
|
|
leaf->ebx = 0x02c0003f;
|
|
leaf->ecx = 0x0000003f;
|
|
leaf->edx = 0x00000000;
|
|
return;
|
|
case 1:
|
|
leaf->eax = 0x1c004122;
|
|
leaf->ebx = 0x01c0003f;
|
|
leaf->ecx = 0x0000003f;
|
|
leaf->edx = 0x00000000;
|
|
return;
|
|
case 2:
|
|
leaf->eax = 0x1c004143;
|
|
leaf->ebx = 0x04c0003f;
|
|
leaf->ecx = 0x000003ff;
|
|
leaf->edx = 0x00000000;
|
|
return;
|
|
case 3:
|
|
leaf->eax = 0x1c03c163;
|
|
leaf->ebx = 0x01c0003f;
|
|
leaf->ecx = 0x00003fff;
|
|
leaf->edx = 0x00000004;
|
|
return;
|
|
default:
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
}
|
|
|
|
// leaf 0x00000005 //
|
|
void tigerlake_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x00000005 - MONITOR/MWAIT Leaf
|
|
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
|
// EAX - Smallest monitor-line size in bytes
|
|
// EBX - Largest monitor-line size in bytes
|
|
// ECX -
|
|
// [31:2] - reserved
|
|
// [1:1] - exit MWAIT even with EFLAGS.IF = 0
|
|
// [0:0] - MONITOR/MWAIT extensions are supported
|
|
// EDX -
|
|
// [03-00] - number of C0 sub C-states supported using MWAIT
|
|
// [07-04] - number of C1 sub C-states supported using MWAIT
|
|
// [11-08] - number of C2 sub C-states supported using MWAIT
|
|
// [15-12] - number of C3 sub C-states supported using MWAIT
|
|
// [19-16] - number of C4 sub C-states supported using MWAIT
|
|
// [31-20] - reserved (MBZ)
|
|
leaf->eax = CACHE_LINE_SIZE;
|
|
leaf->ebx = CACHE_LINE_SIZE;
|
|
leaf->ecx = 3;
|
|
leaf->edx = 0x11121020;
|
|
#else
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
#endif
|
|
}
|
|
|
|
// leaf 0x00000006 //
|
|
void tigerlake_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x00000006 - Thermal and Power Management Leaf
|
|
leaf->eax = 0x0017eff7;
|
|
leaf->ebx = 0x00000002;
|
|
leaf->ecx = 0x00000009;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x00000007 //
|
|
void tigerlake_t::get_std_cpuid_leaf_7(Bit32u subfunction, cpuid_function_t *leaf) const
|
|
{
|
|
switch(subfunction) {
|
|
case 0:
|
|
leaf->eax = 0; /* report max sub-leaf that supported in leaf 7 */
|
|
|
|
// * [0:0] FS/GS BASE access instructions
|
|
// * [1:1] Support for IA32_TSC_ADJUST MSR
|
|
// [2:2] SGX: Intel Software Guard Extensions
|
|
// * [3:3] BMI1: Advanced Bit Manipulation Extensions
|
|
// [4:4] HLE: Hardware Lock Elision
|
|
// * [5:5] AVX2
|
|
// * [6:6] FDP Deprecation
|
|
// * [7:7] SMEP: Supervisor Mode Execution Protection
|
|
// * [8:8] BMI2: Advanced Bit Manipulation Extensions
|
|
// * [9:9] Support for Enhanced REP MOVSB/STOSB
|
|
// * [10:10] Support for INVPCID instruction
|
|
// [11:11] RTM: Restricted Transactional Memory
|
|
// [12:12] Supports Platform Quality of Service Monitoring (PQM) capability
|
|
// * [13:13] Deprecates FPU CS and FPU DS values
|
|
// [14:14] Intel Memory Protection Extensions
|
|
// [15:15] Supports Platform Quality of Service Enforcement (PQE) capability
|
|
// * [16:16] AVX512F instructions support
|
|
// * [17:17] AVX512DQ instructions support
|
|
// * [18:18] RDSEED instruction support
|
|
// * [19:19] ADCX/ADOX instructions support
|
|
// * [20:20] SMAP: Supervisor Mode Access Prevention
|
|
// * [22:21] AVX512IFMA52 instructions support
|
|
// [22:22] reserved
|
|
// * [23:23] CLFLUSHOPT instruction
|
|
// * [24:24] CLWB instruction
|
|
// ! [25:25] Intel Processor Trace
|
|
// [26:26] AVX512PF instructions support
|
|
// [27:27] AVX512ER instructions support
|
|
// * [28:28] AVX512CD instructions support
|
|
// * [29:29] SHA instructions support
|
|
// * [30:30] AVX512BW instructions support
|
|
// * [31:31] AVX512VL variable vector length support
|
|
leaf->ebx = get_std_cpuid_leaf_7_ebx(BX_CPUID_EXT3_ENCHANCED_REP_STRINGS);
|
|
|
|
// [0:0] PREFETCHW1 instruction
|
|
// * [1:1] AVX512 VBMI instructions
|
|
// * [2:2] UMIP: Supports user-mode instruction prevention
|
|
// * [3:3] PKU: Protection keys for user-mode pages
|
|
// [4:4] OSPKE: OS has set CR4.PKE to enable protection keys
|
|
// [5:5] WAITPKG (TPAUSE/UMONITOR/UMWAIT) support
|
|
// * [6:6] AVX512 VBMI2 instructions support
|
|
// * [7:7] CET_SS: Support CET Shadow Stack
|
|
// * [8:8] GFNI instructions support
|
|
// * [9:9] VAES instructions support
|
|
// * [10:10] VPCLMULQDQ instruction support
|
|
// * [11:11] AVX512 VNNI instructions support
|
|
// * [12:12] AVX512 BITALG instructions support
|
|
// [13:13] reserved
|
|
// * [14:14] AVX512 VPOPCNTDQ: AVX512 VPOPCNTD/VPOPCNTQ instructions
|
|
// [15:15] reserved
|
|
// [16:16] LA57: LA57 and 5-level paging
|
|
// [17:17] reserved
|
|
// [18:18] reserved
|
|
// [19:19] reserved
|
|
// [20:20] reserved
|
|
// [21:21] reserved
|
|
// * [22:22] RDPID: Read Processor ID support
|
|
// ! [23:23] Keylocker support
|
|
// [24:24] reserved
|
|
// [25:25] CLDEMOTE: CLDEMOTE instruction support
|
|
// [26:26] reserved
|
|
// ! [27:27] MOVDIRI: MOVDIRI instruction support
|
|
// ! [28:28] MOVDIRI64: MOVDIRI64 instruction support
|
|
// [29:29] ENQCMD: Enqueue Stores support
|
|
// [30:30] SGX_LC: SGX Launch Configuration
|
|
// [31:31] PKS: Protection keys for supervisor-mode pages
|
|
leaf->ecx = get_std_cpuid_leaf_7_ecx();
|
|
|
|
// [0:0] reserved
|
|
// [1:1] reserved
|
|
// [2:2] AVX512_4VNNIW support
|
|
// [3:3] AVX512_4FMAPS support
|
|
// * [4:4] Fast Short REP MOV support
|
|
// [5:5] UINTR: User interrupts support
|
|
// [6:6] reserved
|
|
// [7:7] reserved
|
|
// * [8:8] AVX512_VP2INTERSECT support
|
|
// [9:9] reserved
|
|
// * [10:10] MD clear support
|
|
// [11:11] reserved
|
|
// [12:12] reserved
|
|
// [13:13] reserved
|
|
// [14:14] SERIALIZE instruction support
|
|
// [15:15] Hybrid processor
|
|
// [16:16] TSXLDTRK: TSX suspent load tracking support
|
|
// [17:17] reserved
|
|
// [18:18] PCONFIG support
|
|
// [19:19] reserved
|
|
// * [20:20] CET IBT: Support CET indirect branch tracking
|
|
// [21:21] reserved
|
|
// [22:22] AMX BF16 support
|
|
// [23:23] AVX512_FP16 instructions support
|
|
// [24:24] AMX TILE architecture support
|
|
// [25:25] AMX INT8 support
|
|
// * [26:26] IBRS: indirect branch restricted speculation
|
|
// * [27:27] STIBP: single thread indirect branch predictors
|
|
// * [28:28] L1D_FLUSH support
|
|
// * [29:29] Support for the IA32_ARCH_CAPABILITIES MSR
|
|
// * [30:30] Support for the IA32_CORE_CAPABILITIES MSR
|
|
// * [31:31] SSBD: Speculative Store Bypass Disable
|
|
|
|
leaf->edx = BX_CPUID_EXT5_FAST_SHORT_REP_MOV |
|
|
BX_CPUID_EXT5_AVX512_VPINTERSECT;
|
|
|
|
#if BX_SUPPORT_CET
|
|
leaf->edx |= BX_CPUID_EXT5_CET_IBT;
|
|
#endif
|
|
|
|
if (is_cpu_extension_supported(BX_ISA_SCA_MITIGATIONS))
|
|
leaf->edx |= BX_CPUID_EXT5_MD_CLEAR |
|
|
BX_CPUID_EXT5_SCA_IBRS_IBPB |
|
|
BX_CPUID_EXT5_SCA_STIBP |
|
|
BX_CPUID_EXT5_L1D_FLUSH |
|
|
BX_CPUID_EXT5_ARCH_CAPABILITIES_MSR |
|
|
BX_CPUID_EXT5_CORE_CAPABILITIES_MSR |
|
|
BX_CPUID_EXT5_SCA_SSBD;
|
|
break;
|
|
|
|
default:
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
}
|
|
|
|
// leaf 0x00000008 reserved //
|
|
// leaf 0x00000009 direct cache access not supported //
|
|
|
|
// leaf 0x0000000A //
|
|
void tigerlake_t::get_std_cpuid_leaf_A(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x0000000A - Architectural Performance Monitoring Leaf
|
|
leaf->eax = 0x08300805;
|
|
leaf->ebx = 0x00000000;
|
|
leaf->ecx = 0x0000000f;
|
|
leaf->edx = 0x00008604;
|
|
|
|
BX_INFO(("WARNING: Architectural Performance Monitoring is not implemented"));
|
|
}
|
|
|
|
// leaf 0x0000000C - reserved //
|
|
// leaf 0x0000000D - XSAVE //
|
|
// leaf 0x0000000E - reserved //
|
|
// leaf 0x0000000F - L3 Cache Intel RDT Monitoring Capability Enumeration //
|
|
// leaf 0x00000010 - Intel Resource Director Technology (Intel RDT) Allocation Enumeration //
|
|
// leaf 0x00000011 - reserved //
|
|
// leaf 0x00000012 - Intel Software Guard Extensions //
|
|
// leaf 0x00000013 - reserved //
|
|
// leaf 0x00000014 - Intel Processor Trace Enumeration //
|
|
|
|
// leaf 0x00000015 - Time Stamp Counter and Core Crystal Clock Information Leaf //
|
|
void tigerlake_t::get_std_cpuid_leaf_15(cpuid_function_t *leaf) const
|
|
{
|
|
leaf->eax = 0x00000002;
|
|
leaf->ebx = 0x0000007e;
|
|
leaf->ecx = 0x0249f000;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x00000016 - Processor Frequency Information Leaf
|
|
void tigerlake_t::get_std_cpuid_leaf_16(cpuid_function_t *leaf) const
|
|
{
|
|
leaf->eax = 0x00000960;
|
|
leaf->ebx = 0x00001068;
|
|
leaf->ecx = 0x00000064;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x00000017 - System-On-Chip Vendor Attribute Enumeration //
|
|
|
|
// leaf 0x00000018
|
|
void tigerlake_t::get_std_cpuid_leaf_18(Bit32u subfunction, cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x00000018 - Deterministic Address Translation Parameters
|
|
switch(subfunction) {
|
|
case 0:
|
|
leaf->eax = 0x00000008;
|
|
leaf->ebx = 0x00000000;
|
|
leaf->ecx = 0x00000000;
|
|
leaf->edx = 0x00000000;
|
|
return;
|
|
case 1:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00080001;
|
|
leaf->ecx = 0x00000010;
|
|
leaf->edx = 0x00004022;
|
|
return;
|
|
case 2:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00080006;
|
|
leaf->ecx = 0x00000002;
|
|
leaf->edx = 0x00004022;
|
|
return;
|
|
case 3:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x0010000f;
|
|
leaf->ecx = 0x00000001;
|
|
leaf->edx = 0x00004125;
|
|
return;
|
|
case 4:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00040001;
|
|
leaf->ecx = 0x00000010;
|
|
leaf->edx = 0x00004024;
|
|
return;
|
|
case 5:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00040006;
|
|
leaf->ecx = 0x00000008;
|
|
leaf->edx = 0x00004024;
|
|
return;
|
|
case 6:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00080008;
|
|
leaf->ecx = 0x00000080;
|
|
leaf->edx = 0x00004043;
|
|
return;
|
|
case 7:
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00080009;
|
|
leaf->ecx = 0x00000080;
|
|
leaf->edx = 0x00004043;
|
|
return;
|
|
default:
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
}
|
|
|
|
// leaf 0x80000000 //
|
|
void tigerlake_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
|
|
{
|
|
// EAX: highest extended function understood by CPUID
|
|
// EBX: reserved
|
|
// EDX: reserved
|
|
// ECX: reserved
|
|
get_leaf_0(0x80000008, NULL, leaf);
|
|
}
|
|
|
|
// leaf 0x80000001 //
|
|
void tigerlake_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
|
|
{
|
|
// EAX: CPU Version Information (reserved for Intel)
|
|
leaf->eax = 0;
|
|
|
|
// EBX: Brand ID (reserved for Intel)
|
|
leaf->ebx = 0;
|
|
|
|
// ECX:
|
|
// * [0:0] LAHF/SAHF instructions support in 64-bit mode
|
|
// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
|
|
// [2:2] SVM: Secure Virtual Machine (AMD)
|
|
// [3:3] Extended APIC Space
|
|
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
|
|
// * [5:5] LZCNT: LZCNT instruction support
|
|
// [6:6] SSE4A: SSE4A Instructions support (deprecated?)
|
|
// [7:7] Misaligned SSE support
|
|
// * [8:8] PREFETCHW: PREFETCHW instruction support
|
|
// [9:9] OSVW: OS visible workarounds (AMD)
|
|
// [11:10] reserved
|
|
// [12:12] SKINIT support
|
|
// [13:13] WDT: Watchdog timer support
|
|
// [31:14] reserved
|
|
|
|
leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF |
|
|
BX_CPUID_EXT2_LZCNT |
|
|
BX_CPUID_EXT2_PREFETCHW;
|
|
|
|
// EDX:
|
|
// Many of the bits in EDX are the same as EAX [*] for AMD
|
|
// [10:0] Reserved for Intel
|
|
// * [11:11] SYSCALL/SYSRET support
|
|
// [19:12] Reserved for Intel
|
|
// * [20:20] No-Execute page protection
|
|
// [25:21] Reserved
|
|
// * [26:26] 1G paging support
|
|
// * [27:27] Support RDTSCP Instruction
|
|
// [28:28] Reserved
|
|
// * [29:29] Long Mode
|
|
// [30:30] AMD 3DNow! Extensions
|
|
// [31:31] AMD 3DNow! Instructions
|
|
|
|
leaf->edx = BX_CPUID_STD2_NX |
|
|
BX_CPUID_STD2_1G_PAGES |
|
|
BX_CPUID_STD2_RDTSCP |
|
|
BX_CPUID_STD2_LONG_MODE;
|
|
if (cpu->long64_mode())
|
|
leaf->edx |= BX_CPUID_STD2_SYSCALL_SYSRET;
|
|
}
|
|
|
|
// leaf 0x80000002 //
|
|
// leaf 0x80000003 //
|
|
// leaf 0x80000004 //
|
|
|
|
// leaf 0x80000005 - L1 Cache and TLB Identifiers (reserved for Intel) //
|
|
|
|
// leaf 0x80000006 //
|
|
void tigerlake_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000006 - L2 Cache and TLB Identifiers
|
|
leaf->eax = 0x00000000;
|
|
leaf->ebx = 0x00000000;
|
|
leaf->ecx = 0x01007040;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x80000007 //
|
|
void tigerlake_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000007 - Advanced Power Management
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0x00000100; // bit 8 - invariant TSC
|
|
}
|
|
|
|
// leaf 0x80000008 //
|
|
|
|
void tigerlake_t::dump_cpuid(void) const
|
|
{
|
|
bx_cpuid_t::dump_cpuid(0x18, 0x8);
|
|
}
|
|
|
|
bx_cpuid_t *create_tigerlake_cpuid(BX_CPU_C *cpu) { return new tigerlake_t(cpu); }
|
|
|
|
#endif
|