0730ff4c4a
these are include LOCKed RMW of course and also a lot of others in the future it will be very hard to find all the cases that must be atomic so better to start marking them already now try to mark every RMW case for atomicity requirements no code changes, only comments
146 lines
3.7 KiB
C++
146 lines
3.7 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2018 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EqM(bxInstruction_c *i)
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{
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RSP_SPECULATIVE;
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Bit64u val64 = pop_64();
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// Note: there is one little weirdism here. It is possible to use
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// RSP in the modrm addressing. If used, the value of RSP after the
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// pop is used to calculate the address.
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bx_address eaddr = BX_CPU_RESOLVE_ADDR_64(i);
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write_linear_qword(i->seg(), get_laddr64(i->seg(), eaddr), val64);
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RSP_COMMIT;
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_EqR(bxInstruction_c *i)
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{
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push_64(BX_READ_64BIT_REG(i->dst()));
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EqR(bxInstruction_c *i)
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{
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BX_WRITE_64BIT_REG(i->dst(), pop_64());
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH64_Sw(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[i->src()].selector.value);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP64_Sw(bxInstruction_c *i)
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{
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Bit16u selector = stack_read_word(RSP);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[i->dst()], selector);
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RSP += 8;
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH64_Id(bxInstruction_c *i)
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{
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Bit64u imm64 = (Bit32s) i->Id();
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push_64(imm64);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_EqM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_RESOLVE_ADDR_64(i);
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Bit64u op1_64 = read_linear_qword(i->seg(), get_laddr64(i->seg(), eaddr));
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push_64(op1_64);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ENTER64_IwIb(bxInstruction_c *i)
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{
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Bit8u level = i->Ib2();
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level &= 0x1F;
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Bit64u temp_RSP = RSP, temp_RBP = RBP;
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temp_RSP -= 8;
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stack_write_qword(temp_RSP, temp_RBP);
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Bit64u frame_ptr64 = temp_RSP;
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if (level > 0) {
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/* do level-1 times */
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while (--level) {
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temp_RBP -= 8;
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Bit64u temp64 = stack_read_qword(temp_RBP);
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temp_RSP -= 8;
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stack_write_qword(temp_RSP, temp64);
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} /* while (--level) */
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/* push(frame pointer) */
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temp_RSP -= 8;
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stack_write_qword(temp_RSP, frame_ptr64);
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} /* if (level > 0) ... */
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temp_RSP -= i->Iw();
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// ENTER finishes with memory write check on the final stack pointer
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// the memory is touched but no write actually occurs
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// emulate it by doing RMW read access from SS:RSP
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read_RMW_linear_qword(BX_SEG_REG_SS, temp_RSP); // no lock, should be touch only
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RBP = frame_ptr64;
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RSP = temp_RSP;
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LEAVE64(bxInstruction_c *i)
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{
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// restore frame pointer
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Bit64u temp64 = stack_read_qword(RBP);
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RSP = RBP + 8;
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RBP = temp64;
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BX_NEXT_INSTR(i);
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}
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#endif /* if BX_SUPPORT_X86_64 */
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