519 lines
11 KiB
C++
519 lines
11 KiB
C++
// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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void
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BX_CPU_C::SHLD_EwGw(BxInstruction_t *i)
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{
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Bit16u op1_16, op2_16, result_16;
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Bit32u temp_32, result_32;
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unsigned count;
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/* op1:op2 << count. result stored in op1 */
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if (i->b1 == 0x1a4)
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count = i->Ib;
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else // 0x1a5
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count = CL;
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count &= 0x1f; // use only 5 LSB's
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if (!count) return; /* NOP */
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// count is 1..31
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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op2_16 = BX_READ_16BIT_REG(i->nnn);
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temp_32 = (op1_16 << 16) | (op2_16); // double formed by op1:op2
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result_32 = temp_32 << count;
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if (count > 16) {
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// hack to act like x86 SHLD when count > 16
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// actually shifting op1:op2:op2 << count
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result_32 |= (op2_16 << (count - 16));
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}
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result_16 = result_32 >> 16;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* SHLD count affects the following flags: S,Z,P,C,O
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*/
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set_CF( (temp_32 >> (32 - count)) & 0x01 );
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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set_ZF(result_16 == 0);
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set_SF(result_16 >> 15);
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set_PF_base((Bit8u) result_16);
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}
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void
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BX_CPU_C::SHRD_EwGw(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 3
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bx_panic("shrd_evgvib: not supported on < 386\n");
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#else
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Bit16u op1_16, op2_16, result_16;
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Bit32u temp_32, result_32;
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unsigned count;
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if (i->b1 == 0x1ac)
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count = i->Ib;
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else // 0x1ad
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count = CL;
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count &= 0x1F; /* use only 5 LSB's */
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if (!count) return; /* NOP */
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// count is 1..31
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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op2_16 = BX_READ_16BIT_REG(i->nnn);
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temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1
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result_32 = temp_32 >> count;
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if (count > 16) {
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// hack to act like x86 SHLD when count > 16
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// actually shifting op2:op2:op1 >> count
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result_32 |= (op2_16 << (32 - count));
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}
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result_16 = result_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* SHRD count affects the following flags: S,Z,P,C,O
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*/
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set_CF((temp_32 >> (count - 1)) & 0x01);
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set_ZF(result_16 == 0);
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set_SF(result_16 >> 15);
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/* for shift of 1, OF set if sign change occurred. */
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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set_PF_base((Bit8u) result_16);
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#endif /* BX_CPU_LEVEL >= 3 */
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}
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void
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BX_CPU_C::ROL_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x0f; // only use bottom 4 bits
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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if (count) {
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result_16 = (op1_16 << count) | (op1_16 >> (16 - count));
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* ROL count affects the following flags: C
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*/
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set_CF(result_16 & 0x01);
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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}
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}
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void
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BX_CPU_C::ROR_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16, result_b15;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x0f; // use only 4 LSB's
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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if (count) {
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result_16 = (op1_16 >> count) | (op1_16 << (16 - count));
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* ROR count affects the following flags: C
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*/
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result_b15 = result_16 & 0x8000;
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set_CF(result_b15 != 0);
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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}
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}
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void
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BX_CPU_C::RCL_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x1F;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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count %= 17;
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if (!count) return;
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if (count==1) {
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result_16 = (op1_16 << 1) | get_CF();
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}
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else if (count==16) {
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result_16 = (get_CF() << 15) |
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(op1_16 >> 1);
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}
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else { // 2..15
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result_16 = (op1_16 << count) |
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(get_CF() << (count - 1)) |
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(op1_16 >> (17 - count));
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}
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* RCL count affects the following flags: C
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*/
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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set_CF((op1_16 >> (16 - count)) & 0x01);
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}
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void
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BX_CPU_C::RCR_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count = count & 0x1F;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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count %= 17;
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if (count) {
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result_16 = (op1_16 >> count) |
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(get_CF() << (16 - count)) |
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(op1_16 << (17 - count));
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* RCR count affects the following flags: C
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*/
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set_CF((op1_16 >> (count - 1)) & 0x01);
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if (count == 1)
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set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
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}
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}
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void
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BX_CPU_C::SHL_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x1F; /* use only 5 LSB's */
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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if (!count) return;
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result_16 = (op1_16 << count);
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHL16);
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}
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void
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BX_CPU_C::SHR_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x1F; /* use only 5 LSB's */
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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if (!count) return;
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result_16 = (op1_16 >> count);
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHR16);
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}
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void
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BX_CPU_C::SAR_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16, result_16;
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unsigned count;
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if ( i->b1 == 0xc1 )
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count = i->Ib;
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else if ( i->b1 == 0xd1 )
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count = 1;
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else // 0xd3
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count = CL;
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count &= 0x1F; /* use only 5 LSB's */
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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if (!count) return;
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if (count < 16) {
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if (op1_16 & 0x8000) {
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result_16 = (op1_16 >> count) | (0xffff << (16 - count));
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}
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else {
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result_16 = (op1_16 >> count);
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}
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}
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else {
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if (op1_16 & 0x8000) {
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result_16 = 0xffff;
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}
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else {
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result_16 = 0;
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}
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}
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, result_16);
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}
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else {
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write_RMW_virtual_word(result_16);
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}
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/* set eflags:
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* SAR count affects the following flags: S,Z,P,C
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*/
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if (count < 16) {
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set_CF((op1_16 >> (count - 1)) & 0x01);
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}
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else {
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if (op1_16 & 0x8000) {
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set_CF(1);
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}
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else {
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set_CF(0);
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}
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}
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set_ZF(result_16 == 0);
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set_SF(result_16 >> 15);
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if (count == 1)
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set_OF(0);
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set_PF_base((Bit8u) result_16);
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}
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