388 lines
14 KiB
C++
388 lines
14 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_DISASM
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#include "disasm/disasm.h"
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void BX_CPU_C::debug_disasm_instruction(bx_address offset)
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{
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#if BX_DEBUGGER
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bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
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#else
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bx_phy_address phy_addr;
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Bit8u instr_buf[16];
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char char_buf[512];
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size_t i=0;
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static char letters[] = "0123456789ABCDEF";
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unsigned remainsInPage = 0x1000 - PAGE_OFFSET(offset);
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extern unsigned bx_dbg_disasm_wrapper(bx_bool is_32, bx_bool is_64, bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf);
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static disassembler bx_disassemble;
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bx_bool valid = dbg_xlate_linear2phy(get_laddr(BX_SEG_REG_CS, offset), &phy_addr);
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if (valid) {
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BX_MEM(0)->dbg_fetch_mem(BX_CPU_THIS, phy_addr, 16, instr_buf);
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#if BX_DEBUGGER
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unsigned isize = bx_dbg_disasm_wrapper(
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
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BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64,
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BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS), offset,
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instr_buf, char_buf+i);
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#else
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unsigned isize = bx_disassemble.disasm(
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
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BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64,
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BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS), offset,
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instr_buf, char_buf+i);
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#endif
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if (isize <= remainsInPage) {
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i=strlen(char_buf);
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char_buf[i++] = ' ';
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char_buf[i++] = ':';
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char_buf[i++] = ' ';
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for (unsigned j=0; j<isize; j++) {
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char_buf[i++] = letters[(instr_buf[j] >> 4) & 0xf];
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char_buf[i++] = letters[(instr_buf[j] >> 0) & 0xf];
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}
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char_buf[i] = 0;
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BX_INFO(("0x" FMT_ADDRX ">> %s", offset, char_buf));
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}
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else {
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BX_INFO(("0x" FMT_ADDRX ": (instruction unavailable) page split instruction", offset));
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}
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}
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else {
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BX_INFO(("0x" FMT_ADDRX ": (instruction unavailable) page not present", offset));
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}
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#endif // #if BX_DEBUGGER
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}
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#endif // #if BX_DISASM
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const char* cpu_mode_string(unsigned cpu_mode)
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{
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static const char *cpu_mode_name[] = {
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"real mode",
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"v8086 mode",
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"protected mode",
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"compatibility mode",
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"long mode",
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"unknown mode"
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};
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if(cpu_mode >= 5) cpu_mode = 5;
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return cpu_mode_name[cpu_mode];
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}
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const char* cpu_state_string(unsigned state)
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{
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static const char *cpu_state_name[] = {
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"active",
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"halted",
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"in shutdown",
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"waiting for SIPI",
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"executing mwait",
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"executing mwait inhibit interrupts",
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"unknown state"
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};
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if(state >= 6) state = 6;
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return cpu_state_name[state];
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}
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void BX_CPU_C::debug(bx_address offset)
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{
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#if BX_SUPPORT_VMX
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BX_INFO(("CPU is in %s (%s%s)", cpu_mode_string(BX_CPU_THIS_PTR get_cpu_mode()),
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cpu_state_string(BX_CPU_THIS_PTR activity_state),
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BX_CPU_THIS_PTR in_vmx_guest ? ", vmx guest" : ""));
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#else
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BX_INFO(("CPU is in %s (%s)", cpu_mode_string(BX_CPU_THIS_PTR get_cpu_mode()),
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cpu_state_string(BX_CPU_THIS_PTR activity_state)));
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#endif
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BX_INFO(("CS.mode = %u bit",
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long64_mode() ? 64 : (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b ? 32 : 16)));
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BX_INFO(("SS.mode = %u bit",
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long64_mode() ? 64 : (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b ? 32 : 16)));
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#if BX_CPU_LEVEL >= 5
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BX_INFO(("EFER = 0x%08x", BX_CPU_THIS_PTR efer.get32()));
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#endif
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#if BX_SUPPORT_X86_64
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if (long_mode()) {
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BX_INFO(("| RAX=" FMT_ADDRX64 " RBX=" FMT_ADDRX64 "", RAX, RBX));
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BX_INFO(("| RCX=" FMT_ADDRX64 " RDX=" FMT_ADDRX64 "", RCX, RDX));
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BX_INFO(("| RSP=" FMT_ADDRX64 " RBP=" FMT_ADDRX64 "", RSP, RBP));
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BX_INFO(("| RSI=" FMT_ADDRX64 " RDI=" FMT_ADDRX64 "", RSI, RDI));
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BX_INFO(("| R8=" FMT_ADDRX64 " R9=" FMT_ADDRX64 "", R8, R9));
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BX_INFO(("| R10=" FMT_ADDRX64 " R11=" FMT_ADDRX64 "", R10, R11));
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BX_INFO(("| R12=" FMT_ADDRX64 " R13=" FMT_ADDRX64 "", R12, R13));
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BX_INFO(("| R14=" FMT_ADDRX64 " R15=" FMT_ADDRX64 "", R14, R15));
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}
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else
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#endif
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{
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BX_INFO(("| EAX=%08x EBX=%08x ECX=%08x EDX=%08x", EAX, EBX, ECX, EDX));
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BX_INFO(("| ESP=%08x EBP=%08x ESI=%08x EDI=%08x", ESP, EBP, ESI, EDI));
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}
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BX_INFO(("| IOPL=%1u %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s",
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BX_CPU_THIS_PTR get_IOPL(),
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BX_CPU_THIS_PTR get_ID() ? "ID" : "id",
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BX_CPU_THIS_PTR get_VIP() ? "VIP" : "vip",
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BX_CPU_THIS_PTR get_VIF() ? "VIF" : "vif",
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BX_CPU_THIS_PTR get_AC() ? "AC" : "ac",
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BX_CPU_THIS_PTR get_VM() ? "VM" : "vm",
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BX_CPU_THIS_PTR get_RF() ? "RF" : "rf",
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BX_CPU_THIS_PTR get_NT() ? "NT" : "nt",
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BX_CPU_THIS_PTR get_OF() ? "OF" : "of",
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BX_CPU_THIS_PTR get_DF() ? "DF" : "df",
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BX_CPU_THIS_PTR get_IF() ? "IF" : "if",
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BX_CPU_THIS_PTR get_TF() ? "TF" : "tf",
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BX_CPU_THIS_PTR get_SF() ? "SF" : "sf",
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BX_CPU_THIS_PTR get_ZF() ? "ZF" : "zf",
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BX_CPU_THIS_PTR get_AF() ? "AF" : "af",
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BX_CPU_THIS_PTR get_PF() ? "PF" : "pf",
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BX_CPU_THIS_PTR get_CF() ? "CF" : "cf"));
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BX_INFO(("| SEG sltr(index|ti|rpl) base limit G D"));
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BX_INFO(("| CS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b));
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BX_INFO(("| DS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b));
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BX_INFO(("| SS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b));
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BX_INFO(("| ES:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b));
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BX_INFO(("| FS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.d_b));
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BX_INFO(("| GS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b));
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#if BX_SUPPORT_X86_64
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if (long_mode()) {
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BX_INFO(("| MSR_FS_BASE:" FMT_ADDRX64,
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MSR_FSBASE));
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BX_INFO(("| MSR_GS_BASE:" FMT_ADDRX64,
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MSR_GSBASE));
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BX_INFO(("| RIP=" FMT_ADDRX64 " (" FMT_ADDRX64 ")",
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BX_CPU_THIS_PTR gen_reg[BX_64BIT_REG_RIP].rrx,
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BX_CPU_THIS_PTR prev_rip));
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BX_INFO(("| CR0=0x%08x CR2=0x" FMT_ADDRX64,
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(BX_CPU_THIS_PTR cr0.get32()),
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(BX_CPU_THIS_PTR cr2)));
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BX_INFO(("| CR3=0x" FMT_ADDRX64 " CR4=0x%08x",
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BX_CPU_THIS_PTR cr3, BX_CPU_THIS_PTR cr4.get32()));
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}
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else
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#endif // BX_SUPPORT_X86_64
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{
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BX_INFO(("| EIP=%08x (%08x)", (unsigned) EIP,
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(unsigned) BX_CPU_THIS_PTR prev_rip));
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#if BX_CPU_LEVEL < 5
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BX_INFO(("| CR0=0x%08x CR2=0x%08x CR3=0x%08x",
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(unsigned) BX_CPU_THIS_PTR cr0.get32(),
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(unsigned) BX_CPU_THIS_PTR cr2, (unsigned) BX_CPU_THIS_PTR cr3));
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#else
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BX_INFO(("| CR0=0x%08x CR2=0x%08x",
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BX_CPU_THIS_PTR cr0.get32(), (unsigned) BX_CPU_THIS_PTR cr2));
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BX_INFO(("| CR3=0x%08x CR4=0x%08x",
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(unsigned) BX_CPU_THIS_PTR cr3,
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(unsigned) BX_CPU_THIS_PTR cr4.get32()));
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#endif
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}
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#if BX_DISASM
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debug_disasm_instruction(offset);
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#endif // #if BX_DISASM
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}
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#if BX_DEBUGGER
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void BX_CPU_C::dbg_set_eip(bx_address val)
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{
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RIP = BX_CPU_THIS_PTR prev_rip = val;
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invalidate_prefetch_q();
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}
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bx_bool BX_CPU_C::dbg_set_eflags(Bit32u val)
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{
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// returns 1=OK, 0=can't change
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if (val & 0xffff0000) {
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BX_INFO(("dbg_set_eflags: can't set upper 16 bits of EFLAGS !"));
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return(0);
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}
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// make sure none of the system bits are being changed
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Bit32u current_sys_bits = ((BX_CPU_THIS_PTR getB_NT()) << 14) |
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(BX_CPU_THIS_PTR get_IOPL () << 12) |
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((BX_CPU_THIS_PTR getB_TF()) << 8);
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if (current_sys_bits != (val & 0x0000f100)) {
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BX_INFO(("dbg_set_eflags: can't modify NT, IOPL, or TF !"));
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return(0);
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}
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BX_CPU_THIS_PTR set_CF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_PF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_AF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_ZF(val & 0x01); val >>= 1;
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BX_CPU_THIS_PTR set_SF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_DF(val & 0x01); val >>= 1;
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BX_CPU_THIS_PTR set_OF(val & 0x01);
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return(1);
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}
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unsigned BX_CPU_C::dbg_query_pending(void)
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{
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unsigned ret = 0;
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if (BX_HRQ) { // DMA Hold Request
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ret |= BX_DBG_PENDING_DMA;
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}
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if (is_unmasked_event_pending(BX_EVENT_PENDING_INTR)) {
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ret |= BX_DBG_PENDING_IRQ;
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}
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return ret;
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}
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bx_bool BX_CPU_C::dbg_get_sreg(bx_dbg_sreg_t *sreg, unsigned sreg_no)
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{
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if (sreg_no > 5)
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return(0);
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sreg->valid = BX_CPU_THIS_PTR sregs[sreg_no].cache.valid;
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sreg->sel = BX_CPU_THIS_PTR sregs[sreg_no].selector.value;
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sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
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sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
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#if BX_SUPPORT_X86_64
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sreg->dword3 = BX_CPU_THIS_PTR sregs[sreg_no].cache.u.segment.base >> 32;
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#endif
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return(1);
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}
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bx_bool BX_CPU_C::dbg_set_sreg(unsigned sreg_no, bx_segment_reg_t *sreg)
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{
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if (sreg_no < 6) {
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BX_CPU_THIS_PTR sregs[sreg_no] = *sreg;
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if (sreg_no == BX_SEG_REG_CS) {
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handleCpuModeChange();
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#if BX_CPU_LEVEL >= 4
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handleAlignmentCheck(/* CPL change */);
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#endif
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invalidate_prefetch_q();
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return 1;
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}
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}
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return 0;
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}
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void BX_CPU_C::dbg_get_tr(bx_dbg_sreg_t *sreg)
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{
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sreg->valid = BX_CPU_THIS_PTR tr.cache.valid;
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sreg->sel = BX_CPU_THIS_PTR tr.selector.value;
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sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR tr.cache);
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sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR tr.cache);
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#if BX_SUPPORT_X86_64
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sreg->dword3 = BX_CPU_THIS_PTR tr.cache.u.segment.base >> 32;
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#endif
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}
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void BX_CPU_C::dbg_get_ldtr(bx_dbg_sreg_t *sreg)
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{
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sreg->valid = BX_CPU_THIS_PTR ldtr.cache.valid;
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sreg->sel = BX_CPU_THIS_PTR ldtr.selector.value;
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sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR ldtr.cache);
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sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR ldtr.cache);
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#if BX_SUPPORT_X86_64
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sreg->dword3 = BX_CPU_THIS_PTR ldtr.cache.u.segment.base >> 32;
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#endif
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}
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void BX_CPU_C::dbg_get_gdtr(bx_dbg_global_sreg_t *sreg)
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{
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sreg->base = BX_CPU_THIS_PTR gdtr.base;
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sreg->limit = BX_CPU_THIS_PTR gdtr.limit;
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}
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|
|
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void BX_CPU_C::dbg_get_idtr(bx_dbg_global_sreg_t *sreg)
|
|
{
|
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sreg->base = BX_CPU_THIS_PTR idtr.base;
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|
sreg->limit = BX_CPU_THIS_PTR idtr.limit;
|
|
}
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|
|
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#endif // #if BX_DEBUGGER
|
|
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void BX_CPU_C::atexit(void)
|
|
{
|
|
debug(BX_CPU_THIS_PTR prev_rip);
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|
}
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