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Bochs/bochs/cpu/ctrl_xfer64.cc
Bryce Denney cec9135e9f - Apply patch.replace-Boolean rev 1.3. Every "Boolean" is now changed to a 
"bx_bool" which is always defined as Bit32u on all platforms.  In Carbon
  specific code, Boolean is still used because the Carbon header files
  define it to unsigned char.
- this fixes bug [ 623152 ] MacOSX: Triple Exception Booting win95.
  The bug was that some code in Bochs depends on Boolean to be a
  32 bit value.  (This should be fixed, but I don't know all the places
  where it needs to be fixed yet.)  Because Carbon defined Boolean as
  an unsigned char, Bochs just followed along and used the unsigned char
  definition to avoid compile problems.  This exposed the dependency
  on 32 bit Boolean on MacOS X only and led to major simulation problems,
  that could only be reproduced and debugged on that platform.
- On the mailing list we debated whether to make all Booleans into "bool" or
  our own type.  I chose bx_bool for several reasons.
  1. Unlike C++'s bool, we can guarantee that bx_bool is the same size on all
     platforms, which makes it much less likely to have more platform-specific
     simulation differences in the future.  (I spent hours on a borrowed
     MacOSX machine chasing bug 618388 before discovering that different sized
     Booleans were the problem, and I don't want to repeat that.)
  2. We still have at least one dependency on 32 bit Booleans which must be
     fixed some time, but I don't want to risk introducing new bugs into the
     simulation just before the 2.0 release.

Modified Files:
    bochs.h config.h.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h plugin.cc plugin.h bios/rombios.c cpu/apic.cc
    cpu/arith16.cc cpu/arith32.cc cpu/arith64.cc cpu/arith8.cc
    cpu/cpu.cc cpu/cpu.h cpu/ctrl_xfer16.cc cpu/ctrl_xfer32.cc
    cpu/ctrl_xfer64.cc cpu/data_xfer16.cc cpu/data_xfer32.cc
    cpu/data_xfer64.cc cpu/debugstuff.cc cpu/exception.cc
    cpu/fetchdecode.cc cpu/flag_ctrl_pro.cc cpu/init.cc
    cpu/io_pro.cc cpu/lazy_flags.cc cpu/lazy_flags.h cpu/mult16.cc
    cpu/mult32.cc cpu/mult64.cc cpu/mult8.cc cpu/paging.cc
    cpu/proc_ctrl.cc cpu/segment_ctrl_pro.cc cpu/stack_pro.cc
    cpu/tasking.cc debug/dbg_main.cc debug/debug.h debug/sim2.cc
    disasm/dis_decode.cc disasm/disasm.h doc/docbook/Makefile
    docs-html/cosimulation.html fpu/wmFPUemu_glue.cc
    gui/amigaos.cc gui/beos.cc gui/carbon.cc gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/siminterface.cc gui/siminterface.h
    gui/term.cc gui/win32.cc gui/wx.cc gui/wxmain.cc gui/wxmain.h
    gui/x.cc instrument/example0/instrument.cc
    instrument/example0/instrument.h
    instrument/example1/instrument.cc
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/cdrom.cc iodev/cdrom.h iodev/cdrom_osx.cc iodev/cmos.cc
    iodev/devices.cc iodev/dma.cc iodev/dma.h iodev/eth_arpback.cc
    iodev/eth_packetmaker.cc iodev/eth_packetmaker.h
    iodev/floppy.cc iodev/floppy.h iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/ioapic.cc
    iodev/ioapic.h iodev/iodebug.cc iodev/iodev.h
    iodev/keyboard.cc iodev/keyboard.h iodev/ne2k.h
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pic.h
    iodev/pit.cc iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h
    iodev/sb16.cc iodev/sb16.h iodev/serial.cc iodev/serial.h
    iodev/vga.cc iodev/vga.h memory/memory.h memory/misc_mem.cc
2002-10-25 11:44:41 +00:00

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/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer64.cc,v 1.17 2002-10-25 11:44:34 bdenney Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::RETnear64_Iw(bxInstruction_c *i)
{
Bit16u imm16;
Bit64u temp_RSP;
Bit64u return_RIP;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
temp_RSP = RSP;
imm16 = i->Iw();
//if ( !can_pop(8) ) {
// BX_PANIC(("retnear_iw: can't pop RIP"));
// /* ??? #SS(0) -or #GP(0) */
// }
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
8, CPL==3, BX_READ, &return_RIP);
/* Pentium book says imm16 is number of words ??? */
//if ( !can_pop(8 + imm16) ) {
// BX_PANIC(("retnear_iw: can't release bytes from stack"));
// /* #GP(0) -or #SS(0) ??? */
// }
RIP = return_RIP;
RSP += 8 + imm16; /* ??? should it be 2*imm16 ? */
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::RETnear64(bxInstruction_c *i)
{
Bit64u temp_RSP;
Bit64u return_RIP;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
temp_RSP = RSP;
//if ( !can_pop(8) ) {
// BX_PANIC(("retnear: can't pop RIP"));
// /* ??? #SS(0) -or #GP(0) */
// }
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
8, CPL==3, BX_READ, &return_RIP);
RIP = return_RIP;
RSP += 8;
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::RETfar64_Iw(bxInstruction_c *i)
{
Bit64u rip, rcs_raw;
Bit16s imm16;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
/* ??? is imm16, number of bytes/words depending on operandsize ? */
imm16 = i->Iw();
#if BX_CPU_LEVEL >= 2
if (protected_mode()) {
BX_CPU_THIS_PTR return_protected(i, imm16);
goto done;
}
#endif
pop_64(&rip);
pop_64(&rcs_raw);
RIP = rip;
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) rcs_raw);
RSP += imm16;
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::RETfar64(bxInstruction_c *i)
{
Bit64u rip, rcs_raw;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
#if BX_CPU_LEVEL >= 2
if ( protected_mode() ) {
BX_CPU_THIS_PTR return_protected(i, 0);
goto done;
}
#endif
pop_64(&rip);
pop_64(&rcs_raw); /* 64bit pop, upper 48 bits discarded */
RIP = rip;
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) rcs_raw);
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::CALL_Aq(bxInstruction_c *i)
{
Bit64u new_RIP;
Bit32s disp32;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
disp32 = i->Id();
new_RIP = RIP + disp32;
/* push 64 bit EA of next instruction */
push_64(BX_CPU_THIS_PTR rip);
RIP = new_RIP;
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::CALL64_Ap(bxInstruction_c *i)
{
Bit16u cs_raw;
Bit32u disp32;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
disp32 = i->Id();
cs_raw = i->Iw2();
if (protected_mode()) {
BX_CPU_THIS_PTR call_protected(i, cs_raw, disp32);
goto done;
}
push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_64(BX_CPU_THIS_PTR rip);
RIP = disp32;
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::CALL_Eq(bxInstruction_c *i)
{
Bit64u temp_RSP;
Bit64u op1_64;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
temp_RSP = RSP;
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
push_64(BX_CPU_THIS_PTR rip);
RIP = op1_64;
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::CALL64_Ep(bxInstruction_c *i)
{
Bit16u cs_raw;
Bit64u op1_64;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
/* op1_64 is a register or memory reference */
if (i->modC0()) {
BX_PANIC(("CALL_Ep: op1 is a register"));
}
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
read_virtual_word(i->seg(), RMAddr(i)+8, &cs_raw);
if ( protected_mode() ) {
BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_64);
goto done;
}
push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_64(BX_CPU_THIS_PTR rip);
RIP = op1_64;
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::JMP_Jq(bxInstruction_c *i)
{
invalidate_prefetch_q();
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, RIP);
}
void
BX_CPU_C::JCC_Jq(bxInstruction_c *i)
{
bx_bool condition;
switch (i->b1() & 0x0f) {
case 0x00: /* JO */ condition = get_OF(); break;
case 0x01: /* JNO */ condition = !get_OF(); break;
case 0x02: /* JB */ condition = get_CF(); break;
case 0x03: /* JNB */ condition = !get_CF(); break;
case 0x04: /* JZ */ condition = get_ZF(); break;
case 0x05: /* JNZ */ condition = !get_ZF(); break;
case 0x06: /* JBE */ condition = get_CF() || get_ZF(); break;
case 0x07: /* JNBE */ condition = !get_CF() && !get_ZF(); break;
case 0x08: /* JS */ condition = get_SF(); break;
case 0x09: /* JNS */ condition = !get_SF(); break;
case 0x0A: /* JP */ condition = get_PF(); break;
case 0x0B: /* JNP */ condition = !get_PF(); break;
case 0x0C: /* JL */ condition = getB_SF() != getB_OF(); break;
case 0x0D: /* JNL */ condition = getB_SF() == getB_OF(); break;
case 0x0E: /* JLE */ condition = get_ZF() || (getB_SF() != getB_OF());
break;
case 0x0F: /* JNLE */ condition = (getB_SF() == getB_OF()) &&
!get_ZF();
break;
default:
condition = 0; // For compiler...all targets should set condition.
break;
}
if (condition) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
#ifdef ignore
void
BX_CPU_C::JMP64_Ap(bxInstruction_c *i)
{
Bit64u disp64;
Bit16u cs_raw;
invalidate_prefetch_q();
if (i->os32L()) {
disp64 = (Bit32s) i->Id();
}
else {
disp64 = (Bit16s) i->Iw();
}
cs_raw = i->Iw2();
#if BX_CPU_LEVEL >= 2
if (protected_mode()) {
BX_CPU_THIS_PTR jump_protected(i, cs_raw, disp32);
goto done;
}
#endif
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
RIP = disp64;
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
#endif
void
BX_CPU_C::JMP_Eq(bxInstruction_c *i)
{
Bit64u op1_64;
invalidate_prefetch_q();
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
RIP = op1_64;
BX_INSTR_UCNEAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP, RIP);
}
/* Far indirect jump */
void
BX_CPU_C::JMP64_Ep(bxInstruction_c *i)
{
Bit16u cs_raw;
Bit64u op1_64;
invalidate_prefetch_q();
if (i->modC0()) {
BX_PANIC(("JMP_Ep(): op1 is a register"));
}
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
read_virtual_word(i->seg(), RMAddr(i)+8, &cs_raw);
if ( protected_mode() ) {
BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_64);
goto done;
}
RIP = op1_64;
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
}
void
BX_CPU_C::IRET64(bxInstruction_c *i)
{
Bit32u rip, ecs_raw, eflags;
invalidate_prefetch_q();
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_iret;
BX_CPU_THIS_PTR show_eip = BX_CPU_THIS_PTR rip;
#endif
#if BX_CPU_LEVEL >= 2
if (BX_CPU_THIS_PTR cr0.pe) {
iret_protected(i);
goto done;
}
#endif
done:
BX_INSTR_FAR_BRANCH(CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
}
void
BX_CPU_C::JCXZ64_Jb(bxInstruction_c *i)
{
if (i->as64L()) {
if ( RCX == 0 ) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
else {
if ( ECX == 0 ) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
}
void
BX_CPU_C::LOOPNE64_Jb(bxInstruction_c *i)
{
if (i->as64L()) {
if ( ((--RCX)!=0) && (get_ZF()==0) ) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
else {
if ( ((--ECX)!=0) && (get_ZF()==0) ) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
}
void
BX_CPU_C::LOOPE64_Jb(bxInstruction_c *i)
{
if (i->as64L()) {
if ( ((--RCX)!=0) && (get_ZF()) ) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
else {
if ( ((--ECX)!=0) && get_ZF()) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
}
void
BX_CPU_C::LOOP64_Jb(bxInstruction_c *i)
{
if (i->as64L()) {
if ((--RCX) != 0) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, RIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
else {
if ((--ECX) != 0) {
RIP += (Bit32s) i->Id();
if (i->os32L()==0)
RIP &= 0xffff; // For 16-bit opSize, upper 48 bits of RIP are cleared.
BX_INSTR_CNEAR_BRANCH_TAKEN(CPU_ID, new_EIP);
revalidate_prefetch_q();
}
#if BX_INSTRUMENTATION
else {
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(CPU_ID);
}
#endif
}
}
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