491035fcb2
Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
466 lines
10 KiB
C++
466 lines
10 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: shift32.cc,v 1.7 2002-09-06 21:54:58 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::SHLD_EdGd(BxInstruction_t *i)
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{
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Bit32u op1_32, op2_32, result_32;
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unsigned count;
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/* op1:op2 << count. result stored in op1 */
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if (i->b1 == 0x1a4)
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count = i->Ib & 0x1f;
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else // 0x1a5
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count = CL & 0x1f;
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if (!count) return; /* NOP */
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* SHLD count affects the following flags: S,Z,P,C,O
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*/
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set_CF((op1_32 >> (32 - count)) & 0x01);
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if (count == 1)
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set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
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set_ZF(result_32 == 0);
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set_PF_base(result_32);
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set_SF(result_32 >> 31);
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}
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void
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BX_CPU_C::SHRD_EdGd(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("shrd_evgvib: not supported on < 386"));
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#else
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Bit32u op1_32, op2_32, result_32;
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unsigned count;
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if (i->b1 == 0x1ac)
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count = i->Ib & 0x1f;
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else // 0x1ad
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count = CL & 0x1f;
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if (!count) return; /* NOP */
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* SHRD count affects the following flags: S,Z,P,C,O
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*/
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set_CF((op1_32 >> (count - 1)) & 0x01);
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set_ZF(result_32 == 0);
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set_SF(result_32 >> 31);
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/* for shift of 1, OF set if sign change occurred. */
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if (count == 1)
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set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
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set_PF_base(result_32);
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#endif /* BX_CPU_LEVEL >= 3 */
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}
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void
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BX_CPU_C::ROL_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (count) {
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result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* ROL count affects the following flags: C
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*/
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set_CF(result_32 & 0x01);
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if (count == 1)
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set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
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}
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}
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void
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BX_CPU_C::ROR_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32, result_b31;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (count) {
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result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* ROR count affects the following flags: C
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*/
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result_b31 = result_32 & 0x80000000;
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set_CF(result_b31 != 0);
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if (count == 1)
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set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
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}
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}
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void
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BX_CPU_C::RCL_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (!count) return;
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if (count==1) {
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result_32 = (op1_32 << 1) | get_CF();
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}
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else {
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result_32 = (op1_32 << count) |
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(get_CF() << (count - 1)) |
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(op1_32 >> (33 - count));
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}
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* RCL count affects the following flags: C
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*/
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if (count == 1)
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set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
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set_CF((op1_32 >> (32 - count)) & 0x01);
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}
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void
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BX_CPU_C::RCR_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (!count) return;
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if (count==1) {
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result_32 = (op1_32 >> 1) | (get_CF() << 31);
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}
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else {
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result_32 = (op1_32 >> count) |
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(get_CF() << (32 - count)) |
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(op1_32 << (33 - count));
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}
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* RCR count affects the following flags: C
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*/
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set_CF((op1_32 >> (count - 1)) & 0x01);
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if (count == 1)
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set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
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}
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void
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BX_CPU_C::SHL_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (!count) return;
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result_32 = (op1_32 << count);
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
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}
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void
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BX_CPU_C::SHR_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (!count) return;
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result_32 = (op1_32 >> count);
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHR32);
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}
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void
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BX_CPU_C::SAR_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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unsigned count;
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if (i->b1 == 0xc1)
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count = i->Ib & 0x1f;
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else if (i->b1 == 0xd1)
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count = 1;
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else // (i->b1 == 0xd3)
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count = CL & 0x1f;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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if (!count) return;
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/* count < 32, since only lower 5 bits used */
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if (op1_32 & 0x80000000) {
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result_32 = (op1_32 >> count) | (0xffffffff << (32 - count));
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}
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else {
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result_32 = (op1_32 >> count);
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}
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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/* set eflags:
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* SAR count affects the following flags: S,Z,P,C
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*/
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set_CF((op1_32 >> (count - 1)) & 0x01);
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set_ZF(result_32 == 0);
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set_SF(result_32 >> 31);
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if (count == 1)
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set_OF(0);
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set_PF_base(result_32);
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}
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