171 lines
9.3 KiB
C++
171 lines
9.3 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011-2023 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_AVX
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#include "softfloat3e/include/softfloat.h"
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extern softfloat_status_t mxcsr_to_softfloat_status_word(bx_mxcsr_t mxcsr);
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#include "simd_pfp.h"
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//////////////////////////
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// AVX FMA Instructions //
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//////////////////////////
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#define AVX2_FMA_SCALAR_SINGLE(HANDLER, func) \
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void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1()); \
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2()); \
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float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3()); \
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\
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softfloat_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1 = (func)(op1, op2, op3, &status); \
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check_exceptionsSSE(softfloat_getExceptionFlags(&status)); \
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\
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BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1); \
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BX_CLEAR_AVX_HIGH128(i->dst()); \
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\
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BX_NEXT_INSTR(i); \
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}
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AVX2_FMA_SCALAR_SINGLE(VFMADDSS_VpsHssWssR, f32_fmadd)
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AVX2_FMA_SCALAR_SINGLE(VFMSUBSS_VpsHssWssR, f32_fmsub)
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AVX2_FMA_SCALAR_SINGLE(VFNMADDSS_VpsHssWssR, f32_fnmadd)
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AVX2_FMA_SCALAR_SINGLE(VFNMSUBSS_VpsHssWssR, f32_fnmsub)
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#define AVX2_FMA_SCALAR_DOUBLE(HANDLER, func) \
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void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1()); \
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2()); \
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3()); \
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\
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softfloat_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1 = (func)(op1, op2, op3, &status); \
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check_exceptionsSSE(softfloat_getExceptionFlags(&status)); \
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\
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BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1); \
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BX_CLEAR_AVX_HIGH128(i->dst()); \
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\
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BX_NEXT_INSTR(i); \
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}
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AVX2_FMA_SCALAR_DOUBLE(VFMADDSD_VpdHsdWsdR, f64_fmadd)
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AVX2_FMA_SCALAR_DOUBLE(VFMSUBSD_VpdHsdWsdR, f64_fmsub)
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AVX2_FMA_SCALAR_DOUBLE(VFNMADDSD_VpdHsdWsdR, f64_fnmadd)
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AVX2_FMA_SCALAR_DOUBLE(VFNMSUBSD_VpdHsdWsdR, f64_fnmsub)
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#if BX_SUPPORT_EVEX
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#define AVX2_FMA_SCALAR_HALF_PRECISION(HANDLER, func) \
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void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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float16 op1 = BX_READ_XMM_REG_LO_WORD(i->src1()); \
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float16 op2 = BX_READ_XMM_REG_LO_WORD(i->src2()); \
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float16 op3 = BX_READ_XMM_REG_LO_WORD(i->src3()); \
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\
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softfloat_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1 = (func)(op1, op2, op3, &status); \
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check_exceptionsSSE(softfloat_getExceptionFlags(&status)); \
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\
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BX_WRITE_XMM_REG_LO_WORD(i->dst(), op1); \
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BX_CLEAR_AVX_HIGH128(i->dst()); \
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\
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BX_NEXT_INSTR(i); \
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}
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AVX2_FMA_SCALAR_HALF_PRECISION(VFMADDSH_VphHshWshR, f16_fmadd)
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AVX2_FMA_SCALAR_HALF_PRECISION(VFMSUBSH_VphHshWshR, f16_fmsub)
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AVX2_FMA_SCALAR_HALF_PRECISION(VFNMADDSH_VphHshWshR, f16_fnmadd)
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AVX2_FMA_SCALAR_HALF_PRECISION(VFNMSUBSH_VphHshWshR, f16_fnmsub)
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#endif
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//////////////////////////////////
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// FMA4 (AMD) specific handlers //
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//////////////////////////////////
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#define FMA4_SINGLE_SCALAR(HANDLER, func) \
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void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1()); \
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2()); \
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float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3()); \
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\
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softfloat_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
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\
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BxPackedXmmRegister dest; \
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dest.xmm64u(0) = (func)(op1, op2, op3, &status); \
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dest.xmm64u(1) = 0; \
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\
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check_exceptionsSSE(softfloat_getExceptionFlags(&status)); \
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\
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BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dest); \
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\
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BX_NEXT_INSTR(i); \
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}
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FMA4_SINGLE_SCALAR(VFMADDSS_VssHssWssVIbR, f32_fmadd)
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FMA4_SINGLE_SCALAR(VFMSUBSS_VssHssWssVIbR, f32_fmsub)
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FMA4_SINGLE_SCALAR(VFNMADDSS_VssHssWssVIbR, f32_fnmadd)
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FMA4_SINGLE_SCALAR(VFNMSUBSS_VssHssWssVIbR, f32_fnmsub)
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#define FMA4_DOUBLE_SCALAR(HANDLER, func) \
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void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1()); \
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2()); \
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3()); \
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\
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softfloat_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
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\
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BxPackedXmmRegister dest; \
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dest.xmm64u(0) = (func)(op1, op2, op3, &status); \
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dest.xmm64u(1) = 0; \
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\
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check_exceptionsSSE(softfloat_getExceptionFlags(&status)); \
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\
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BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dest); \
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\
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BX_NEXT_INSTR(i); \
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}
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FMA4_DOUBLE_SCALAR(VFMADDSD_VsdHsdWsdVIbR, f64_fmadd)
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FMA4_DOUBLE_SCALAR(VFMSUBSD_VsdHsdWsdVIbR, f64_fmsub)
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FMA4_DOUBLE_SCALAR(VFNMADDSD_VsdHsdWsdVIbR, f64_fnmadd)
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FMA4_DOUBLE_SCALAR(VFNMSUBSD_VsdHsdWsdVIbR, f64_fnmsub)
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#endif
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