Stanislav Shwartsman b6e284b080 fix MSVC warnings		2021-02-11 15:05:06 +00:00
..
decoder.h	implemented AVX encoded VNNI instructions published in recent SDM - not tested yet	2020-10-03 09:23:28 +00:00
disasm.cc	! CPUID: Added TigerLake CPU definition (features CET and CLWB support)	2021-01-30 08:35:35 +00:00
fetchdecode32.cc	fix MSVC warnings	2021-02-11 15:05:06 +00:00
fetchdecode64.cc	fixed some MSVC wannings in CPU code	2021-02-08 13:06:44 +00:00
fetchdecode_avx.h	implemented AVX encoded VNNI instructions published in recent SDM - not tested yet	2020-10-03 09:23:28 +00:00
fetchdecode_evex.h	AVX512: VPBROADCASTB/W/D/Q with GPR source are only reg/reg	2019-12-21 18:29:51 +00:00
fetchdecode_opmap_0f3a.h	fix decoder: SHA1RNDS4 instruction should be with no SSE prefix	2019-12-27 13:08:20 +00:00
fetchdecode_opmap_0f38.h	Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071	2019-12-20 07:42:07 +00:00
fetchdecode_opmap.h	Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071	2019-12-20 07:42:07 +00:00
fetchdecode_x87.h	fix disasm of FISTTP opcodes	2017-12-19 20:36:55 +00:00
fetchdecode_xop.h	enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore	2019-02-16 15:23:24 +00:00
fetchdecode.h	fixed disasm of shift/rotate with implicit shift count=1	2021-01-02 15:12:29 +00:00
ia_opcodes.def	implemented AVX encoded VNNI instructions published in recent SDM - not tested yet	2020-10-03 09:23:28 +00:00
ia_opcodes.h	add into ia_opcodes.def disasm field for every instruction	2020-03-28 14:23:54 +00:00
instr.h	! CPUID: Added TigerLake CPU definition (features CET and CLWB support)	2021-01-30 08:35:35 +00:00