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Bochs/bochs/cpu
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Bryce Denney ac4e5bb6cf - add sanity checks 
- don't allow MMX on cpu level < 5.
  - require FPU support on cpu level >= 55
  - don't allow MMX support without FPU support (moved this check from
    cpu/i387.h to config.h)
2002-09-22 16:11:12 +00:00
..
access.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
apic.cc
…
arith8.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
arith16.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
arith32.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
arith64.cc
Modified the way that the register field (low 3 bits of a few opcodes
2002-09-20 23:17:51 +00:00
bcd.cc
…
bit.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
cpu.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
cpu.h
- add typecast to Bit32u to avoid lots of useless -Wall warnings. The constant
2002-09-22 02:53:09 +00:00
ctrl_xfer8.cc
…
ctrl_xfer16.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
ctrl_xfer32.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
ctrl_xfer64.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
ctrl_xfer_pro.cc
…
data_xfer8.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
data_xfer16.cc
Modified the way that the register field (low 3 bits of a few opcodes
2002-09-20 23:17:51 +00:00
data_xfer32.cc
Modified the way that the register field (low 3 bits of a few opcodes
2002-09-20 23:17:51 +00:00
data_xfer64.cc
from Peter Tattam: in MOVSX_GqEd, typecast op2 to Bit32s instead of Bit16s
2002-09-22 15:42:09 +00:00
debugstuff.cc
…
exception.cc
…
extdb.cc
Oops, I had #ifdef 0'd the code in here to do a test compile,
2002-09-22 02:07:46 +00:00
extdb.h
…
fetchdecode64.cc
- from Peter Tattam: fixed invalid instructions for 64 bit mode
2002-09-22 15:29:51 +00:00
fetchdecode.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
flag_ctrl_pro.cc
…
flag_ctrl.cc
…
i387.h
- add sanity checks
2002-09-22 16:11:12 +00:00
init.cc
- Added an instruction cache. Size is fixed for the moment,
2002-09-19 19:17:20 +00:00
io_pro.cc
…
io.cc
- Added an instruction cache. Size is fixed for the moment,
2002-09-19 19:17:20 +00:00
lazy_flags.cc
Split out JZ/JNZ instructions from JCC because they were called
2002-09-22 01:52:21 +00:00
lazy_flags.h
…
logical8.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
logical16.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
logical32.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
logical64.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
Makefile.in
- fixed "macro expands to nothing" by renaming the macro
2002-09-22 07:23:26 +00:00
mmx.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
mult8.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
mult16.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
mult32.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
mult64.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
paging.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
proc_ctrl.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
protect_ctrl_pro.cc
…
protect_ctrl.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
resolve16.cc
- Added an instruction cache. Size is fixed for the moment,
2002-09-19 19:17:20 +00:00
resolve32.cc
- Added an instruction cache. Size is fixed for the moment,
2002-09-19 19:17:20 +00:00
resolve64.cc
…
segment_ctrl_pro.cc
- Added an instruction cache. Size is fixed for the moment,
2002-09-19 19:17:20 +00:00
segment_ctrl.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
shift8.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
shift16.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
shift32.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
shift64.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
soft_int.cc
Moved the EFLAGS.RF check and clearing of inhibit_mask code
2002-09-20 03:52:59 +00:00
stack16.cc
Modified the way that the register field (low 3 bits of a few opcodes
2002-09-20 23:17:51 +00:00
stack32.cc
Modified the way that the register field (low 3 bits of a few opcodes
2002-09-20 23:17:51 +00:00
stack64.cc
Modified the way that the register field (low 3 bits of a few opcodes
2002-09-20 23:17:51 +00:00
stack_pro.cc
…
string.cc
- Added an instruction cache. Size is fixed for the moment,
2002-09-19 19:17:20 +00:00
tasking.cc
…
vm8086.cc
…