a17d06abcb
check. Commented out a number of instances of invalidate_prefetch_q(), for branches which do not change CS since the EIP window mechanism takes care of validating that EIP lands in the current page or not in the main cpu loop anyways. Fixed a couple cases (v8086 mode and real mode) of loading CS where the EIP page window was not invalidated in segment_ctrl_pro.cc. That may fix some aliasing problems reported before (OS2).
540 lines
12 KiB
C++
540 lines
12 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer16.cc,v 1.20 2003-05-10 22:25:51 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::RETnear16_Iw(bxInstruction_c *i)
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{
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BailBigRSP("RETnear16_Iw");
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Bit16u imm16;
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Bit16u return_IP;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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imm16 = i->Iw();
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pop_16(&return_IP);
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if (protected_mode()) {
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if ( return_IP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("retnear_iw: IP > limit"));
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}
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}
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EIP = return_IP;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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ESP += imm16; /* ??? should it be 2*imm16 ? */
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else
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SP += imm16;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
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}
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void
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BX_CPU_C::RETnear16(bxInstruction_c *i)
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{
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BailBigRSP("RETnear16");
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Bit16u return_IP;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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pop_16(&return_IP);
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if (protected_mode()) {
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if ( return_IP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("retnear: IP > limit"));
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}
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}
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EIP = return_IP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
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}
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void
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BX_CPU_C::RETfar16_Iw(bxInstruction_c *i)
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{
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BailBigRSP("RETfar16_Iw");
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Bit16s imm16;
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Bit16u ip, cs_raw;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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/* ??? is imm16, number of bytes/words depending on operandsize ? */
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imm16 = i->Iw();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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BX_CPU_THIS_PTR return_protected(i, imm16);
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goto done;
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}
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#endif
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pop_16(&ip);
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pop_16(&cs_raw);
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EIP = (Bit32u) ip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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ESP += imm16;
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else
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SP += imm16;
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::RETfar16(bxInstruction_c *i)
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{
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BailBigRSP("RETfar16");
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Bit16u ip, cs_raw;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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#if BX_CPU_LEVEL >= 2
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR return_protected(i, 0);
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goto done;
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}
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#endif
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pop_16(&ip);
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pop_16(&cs_raw);
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EIP = (Bit32u) ip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::CALL_Aw(bxInstruction_c *i)
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{
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BailBigRSP("CALL_Aw");
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Bit32u new_EIP;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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new_EIP = EIP + (Bit32s) i->Id();
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new_EIP &= 0x0000ffff;
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#if BX_CPU_LEVEL >= 2
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if ( protected_mode() &&
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(new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) ) {
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BX_PANIC(("call_av: new_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].limit"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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#endif
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/* push 16 bit EA of next instruction */
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push_16(IP);
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EIP = new_EIP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void
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BX_CPU_C::CALL16_Ap(bxInstruction_c *i)
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{
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BailBigRSP("CALL16_Ap");
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Bit16u cs_raw;
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Bit16u disp16;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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disp16 = i->Iw();
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cs_raw = i->Iw2();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, disp16);
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goto done;
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}
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#endif
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push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_16((Bit16u) EIP);
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EIP = (Bit32u) disp16;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::CALL_Ew(bxInstruction_c *i)
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{
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BailBigRSP("CALL_Ew");
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Bit16u op1_16;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if (op1_16 >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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BX_PANIC(("call_ev: IP out of CS limits!"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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push_16(IP);
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EIP = op1_16;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void
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BX_CPU_C::CALL16_Ep(bxInstruction_c *i)
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{
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BailBigRSP("CALL_16_Ep");
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Bit16u cs_raw;
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Bit16u op1_16;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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if (i->modC0()) {
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BX_PANIC(("CALL_Ep: op1 is a register"));
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}
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read_virtual_word(i->seg(), RMAddr(i), &op1_16);
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read_virtual_word(i->seg(), RMAddr(i)+2, &cs_raw);
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_16);
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goto done;
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}
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push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_16(IP);
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EIP = op1_16;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::JMP_Jw(bxInstruction_c *i)
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{
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BailBigRSP("JMP_Jw");
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Bit32u new_EIP;
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//invalidate_prefetch_q();
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new_EIP = EIP + (Bit32s) i->Id();
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new_EIP &= 0x0000ffff;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jmp_jv: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
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}
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void
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BX_CPU_C::JCC_Jw(bxInstruction_c *i)
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{
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BailBigRSP("JCC_Jw");
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bx_bool condition;
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switch (i->b1() & 0x0f) {
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case 0x00: /* JO */ condition = get_OF(); break;
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case 0x01: /* JNO */ condition = !get_OF(); break;
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case 0x02: /* JB */ condition = get_CF(); break;
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case 0x03: /* JNB */ condition = !get_CF(); break;
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case 0x04: /* JZ */ condition = get_ZF(); break;
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case 0x05: /* JNZ */ condition = !get_ZF(); break;
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case 0x06: /* JBE */ condition = get_CF() || get_ZF(); break;
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case 0x07: /* JNBE */ condition = !get_CF() && !get_ZF(); break;
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case 0x08: /* JS */ condition = get_SF(); break;
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case 0x09: /* JNS */ condition = !get_SF(); break;
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case 0x0A: /* JP */ condition = get_PF(); break;
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case 0x0B: /* JNP */ condition = !get_PF(); break;
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case 0x0C: /* JL */ condition = getB_SF() != getB_OF(); break;
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case 0x0D: /* JNL */ condition = getB_SF() == getB_OF(); break;
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case 0x0E: /* JLE */ condition = get_ZF() || (getB_SF() != getB_OF());
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break;
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case 0x0F: /* JNLE */ condition = (getB_SF() == getB_OF()) &&
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!get_ZF();
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break;
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default:
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condition = 0; // For compiler...all targets should set condition.
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break;
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}
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if (condition) {
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Bit32u new_EIP;
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new_EIP = EIP + (Bit32s) i->Id();
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new_EIP &= 0x0000ffff;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jo_routine: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void
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BX_CPU_C::JZ_Jw(bxInstruction_c *i)
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{
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BailBigRSP("JZ_Jw");
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if (get_ZF()) {
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Bit32u new_EIP;
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new_EIP = EIP + (Bit32s) i->Id();
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new_EIP &= 0x0000ffff;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jo_routine: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void
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BX_CPU_C::JNZ_Jw(bxInstruction_c *i)
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{
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BailBigRSP("JNZ_Jw");
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if (!get_ZF()) {
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Bit32u new_EIP;
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new_EIP = EIP + (Bit32s) i->Id();
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new_EIP &= 0x0000ffff;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jo_routine: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void
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BX_CPU_C::JMP_Ew(bxInstruction_c *i)
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{
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BailBigRSP("JMP_Ew");
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Bit32u new_EIP;
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Bit16u op1_16;
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//invalidate_prefetch_q();
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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new_EIP = op1_16;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if (new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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BX_PANIC(("jmp_ev: IP out of CS limits!"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
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}
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/* Far indirect jump */
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void
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BX_CPU_C::JMP16_Ep(bxInstruction_c *i)
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{
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BailBigRSP("JMP16_Ep");
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Bit16u cs_raw;
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Bit16u op1_16;
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invalidate_prefetch_q();
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if (i->modC0()) {
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/* far indirect must specify a memory address */
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BX_PANIC(("JMP_Ep(): op1 is a register"));
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}
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read_virtual_word(i->seg(), RMAddr(i), &op1_16);
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read_virtual_word(i->seg(), RMAddr(i)+2, &cs_raw);
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#if BX_CPU_LEVEL >= 2
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_16);
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goto done;
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}
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#endif
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EIP = op1_16;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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|
|
done:
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::IRET16(bxInstruction_c *i)
|
|
{
|
|
BailBigRSP("IRET16");
|
|
Bit16u ip, cs_raw, flags;
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR show_flag |= Flag_iret;
|
|
BX_CPU_THIS_PTR show_eip = EIP;
|
|
#endif
|
|
|
|
if (v8086_mode()) {
|
|
// IOPL check in stack_return_from_v86()
|
|
stack_return_from_v86(i);
|
|
goto done;
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 2
|
|
if (BX_CPU_THIS_PTR cr0.pe) {
|
|
iret_protected(i);
|
|
goto done;
|
|
}
|
|
#endif
|
|
|
|
|
|
pop_16(&ip);
|
|
pop_16(&cs_raw);
|
|
pop_16(&flags);
|
|
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
|
|
EIP = (Bit32u) ip;
|
|
write_flags(flags, /* change IOPL? */ 1, /* change IF? */ 1);
|
|
|
|
done:
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
}
|