e312454851
- use 'pci_rom_size - 1' as the mask for the offset address - ne2k: memory handlers must be disabled if compiled without PCI support - svga_cirrus: check for the PCI ROM size to make VBE work correctly - added BX_INFO to the mem write handlers
593 lines
17 KiB
C++
593 lines
17 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2003 Fen Systems Ltd.
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// http://www.fensystems.co.uk/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI && BX_SUPPORT_PCIPNIC
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#include "pci.h"
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#include "netmod.h"
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#include "pcipnic.h"
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#define LOG_THIS thePNICDevice->
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bx_pcipnic_c* thePNICDevice = NULL;
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const Bit8u pnic_iomask[16] = {2, 0, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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int libpcipnic_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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thePNICDevice = new bx_pcipnic_c();
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePNICDevice, BX_PLUGIN_PCIPNIC);
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return 0; // Success
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}
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void libpcipnic_LTX_plugin_fini(void)
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{
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delete thePNICDevice;
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}
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bx_pcipnic_c::bx_pcipnic_c()
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{
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put("PNIC");
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}
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bx_pcipnic_c::~bx_pcipnic_c()
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{
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BX_DEBUG(("Exit"));
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}
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void bx_pcipnic_c::init(void)
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{
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bx_list_c *base;
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const char *bootrom;
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// Read in values from config interface
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base = (bx_list_c*) SIM->get_param(BXPN_PNIC);
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memcpy(BX_PNIC_THIS s.macaddr, SIM->get_param_string("macaddr", base)->getptr(), 6);
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BX_PNIC_THIS s.devfunc = 0x00;
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DEV_register_pci_handlers(this, &BX_PNIC_THIS s.devfunc, BX_PLUGIN_PCIPNIC,
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"Experimental PCI Pseudo NIC");
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for (unsigned i=0; i<256; i++) {
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BX_PNIC_THIS pci_conf[i] = 0x0;
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}
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// Attach to the selected ethernet module
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BX_PNIC_THIS ethdev = DEV_net_init_module(base, rx_handler, rx_status_handler, this);
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BX_PNIC_THIS pci_base_address[4] = 0;
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BX_PNIC_THIS pci_rom_address = 0;
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bootrom = SIM->get_param_string("bootrom", base)->getptr();
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if (strlen(bootrom) > 0) {
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BX_PNIC_THIS load_pci_rom(bootrom);
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}
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BX_INFO(("PCI Pseudo NIC initialized"));
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}
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void bx_pcipnic_c::reset(unsigned type)
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{
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unsigned i;
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static const struct reset_vals_t {
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unsigned addr;
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unsigned char val;
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} reset_vals[] = {
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{ 0x00, PNIC_PCI_VENDOR & 0xff },
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{ 0x01, PNIC_PCI_VENDOR >> 8 },
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{ 0x02, PNIC_PCI_DEVICE & 0xff },
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{ 0x03, PNIC_PCI_DEVICE >> 8 },
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{ 0x04, 0x01 }, { 0x05, 0x00 }, // command_io
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{ 0x06, 0x00 }, { 0x07, 0x00 }, // status
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{ 0x08, 0x01 }, // revision number
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{ 0x09, 0x00 }, // interface
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{ 0x0a, 0x00 }, // class_sub
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{ 0x0b, 0x02 }, // class_base Network Controller
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{ 0x0D, 0x20 }, // bus latency
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{ 0x0e, 0x00 }, // header_type_generic
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// address space 0x20 - 0x23
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{ 0x20, 0x01 }, { 0x21, 0x00 },
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{ 0x22, 0x00 }, { 0x23, 0x00 },
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{ 0x3c, 0x00, }, // IRQ
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{ 0x3d, BX_PCI_INTA }, // INT
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{ 0x6a, 0x01 }, // PNIC clock
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{ 0xc1, 0x20 } // PIRQ enable
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};
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for (i = 0; i < sizeof(reset_vals) / sizeof(*reset_vals); ++i) {
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BX_PNIC_THIS pci_conf[reset_vals[i].addr] = reset_vals[i].val;
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}
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// Set up initial register values
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BX_PNIC_THIS s.rCmd = PNIC_CMD_NOOP;
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BX_PNIC_THIS s.rStatus = PNIC_STATUS_OK;
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BX_PNIC_THIS s.rLength = 0;
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BX_PNIC_THIS s.rDataCursor = 0;
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BX_PNIC_THIS s.recvIndex = 0;
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BX_PNIC_THIS s.recvQueueLength = 0;
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BX_PNIC_THIS s.irqEnabled = 0;
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// Deassert IRQ
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set_irq_level(0);
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}
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void bx_pcipnic_c::register_state(void)
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{
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unsigned i;
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char name[6];
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pcipnic", "PCI Pseudo NIC State", 11);
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new bx_shadow_num_c(list, "irqEnabled", &BX_PNIC_THIS s.irqEnabled);
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new bx_shadow_num_c(list, "rCmd", &BX_PNIC_THIS s.rCmd);
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new bx_shadow_num_c(list, "rStatus", &BX_PNIC_THIS s.rStatus);
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new bx_shadow_num_c(list, "rLength", &BX_PNIC_THIS s.rLength);
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new bx_shadow_num_c(list, "rDataCursor", &BX_PNIC_THIS s.rDataCursor);
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new bx_shadow_num_c(list, "recvIndex", &BX_PNIC_THIS s.recvIndex);
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new bx_shadow_num_c(list, "recvQueueLength", &BX_PNIC_THIS s.recvQueueLength);
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bx_list_c *recvRL = new bx_list_c(list, "recvRingLength", PNIC_RECV_RINGS);
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for (i=0; i<PNIC_RECV_RINGS; i++) {
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sprintf(name, "%d", i);
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new bx_shadow_num_c(recvRL, name, &BX_PNIC_THIS s.recvRingLength[i]);
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}
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new bx_shadow_data_c(list, "rData", BX_PNIC_THIS s.rData, PNIC_DATA_SIZE);
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new bx_shadow_data_c(list, "recvRing", (Bit8u*)BX_PNIC_THIS s.recvRing, PNIC_RECV_RINGS*PNIC_DATA_SIZE);
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register_pci_state(list);
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}
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void bx_pcipnic_c::after_restore_state(void)
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{
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if (DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
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&BX_PNIC_THIS pci_base_address[4],
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&BX_PNIC_THIS pci_conf[0x20],
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16, &pnic_iomask[0], "PNIC")) {
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BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS pci_base_address[4]));
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}
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if (BX_PNIC_THIS pci_rom_size > 0) {
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if (DEV_pci_set_base_mem(BX_PNIC_THIS_PTR, mem_read_handler,
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mem_write_handler,
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&BX_PNIC_THIS pci_rom_address,
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&BX_PNIC_THIS pci_conf[0x30],
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BX_PNIC_THIS pci_rom_size)) {
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BX_INFO(("new ROM address: 0x%08x", BX_PNIC_THIS pci_rom_address));
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}
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}
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}
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void bx_pcipnic_c::set_irq_level(bx_bool level)
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{
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DEV_pci_set_irq(BX_PNIC_THIS s.devfunc, BX_PNIC_THIS pci_conf[0x3d], level);
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}
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bx_bool bx_pcipnic_c::mem_read_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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{
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Bit8u *data_ptr;
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Bit32u mask = (BX_PNIC_THIS pci_rom_size - 1);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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for (unsigned i = 0; i < len; i++) {
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if (BX_PNIC_THIS pci_conf[0x30] & 0x01) {
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*data_ptr = BX_PNIC_THIS pci_rom[addr & mask];
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} else {
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*data_ptr = 0xff;
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}
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addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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}
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return 1;
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}
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bx_bool bx_pcipnic_c::mem_write_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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{
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BX_INFO(("write to ROM ignored (addr=0x%08x len=%d)", (Bit32u)addr, len));
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return 1;
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u bx_pcipnic_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_PCIPNIC_SMF
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bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) this_ptr;
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return class_ptr->read(address, io_len);
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}
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Bit32u bx_pcipnic_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCIPNIC_SMF
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Bit32u val = 0x0;
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Bit8u offset;
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BX_DEBUG(("register read from address 0x%04x - ", (unsigned) address));
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offset = address - BX_PNIC_THIS pci_base_address[4];
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switch (offset) {
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case PNIC_REG_STAT:
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val = BX_PNIC_THIS s.rStatus;
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break;
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case PNIC_REG_LEN:
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val = BX_PNIC_THIS s.rLength;
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break;
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case PNIC_REG_DATA:
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if (BX_PNIC_THIS s.rDataCursor >= BX_PNIC_THIS s.rLength)
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BX_PANIC(("PNIC read at %u, beyond end of data register array",
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BX_PNIC_THIS s.rDataCursor));
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val = BX_PNIC_THIS s.rData[BX_PNIC_THIS s.rDataCursor++];
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break;
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default :
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val = 0; // keep compiler happy
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BX_PANIC(("unsupported io read from address=0x%04x!", (unsigned) address));
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break;
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}
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BX_DEBUG(("val = 0x%04x", (Bit16u) val));
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return(val);
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void bx_pcipnic_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PCIPNIC_SMF
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bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void bx_pcipnic_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCIPNIC_SMF
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Bit8u offset;
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BX_DEBUG(("register write to address 0x%04x - ", (unsigned) address));
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offset = address - BX_PNIC_THIS pci_base_address[4];
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switch (offset) {
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case PNIC_REG_CMD:
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BX_PNIC_THIS s.rCmd = value;
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BX_PNIC_THIS exec_command();
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break;
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case PNIC_REG_LEN:
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if (value > PNIC_DATA_SIZE)
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BX_PANIC(("PNIC bad length %u written to length register, max is %u",
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value, PNIC_DATA_SIZE));
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BX_PNIC_THIS s.rLength = value;
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BX_PNIC_THIS s.rDataCursor = 0;
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break;
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case PNIC_REG_DATA:
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if (BX_PNIC_THIS s.rDataCursor >= BX_PNIC_THIS s.rLength)
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BX_PANIC(("PNIC write at %u, beyond end of data register array",
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BX_PNIC_THIS s.rDataCursor));
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BX_PNIC_THIS s.rData[BX_PNIC_THIS s.rDataCursor++] = value;
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break;
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default:
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BX_PANIC(("unsupported io write to address=0x%04x!", (unsigned) address));
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break;
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}
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}
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void bx_pcipnic_c::pnic_timer_handler(void *this_ptr)
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{
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bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) this_ptr;
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class_ptr->pnic_timer();
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}
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// Called once every 1ms
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void bx_pcipnic_c::pnic_timer(void)
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{
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// Do nothing atm
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}
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// pci configuration space read callback handler
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Bit32u bx_pcipnic_c::pci_read_handler(Bit8u address, unsigned io_len)
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{
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Bit32u value = 0;
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for (unsigned i=0; i<io_len; i++) {
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value |= (BX_PNIC_THIS pci_conf[address+i] << (i*8));
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}
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if (io_len == 1)
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BX_DEBUG(("read PCI register 0x%02x value 0x%02x", address, value));
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else if (io_len == 2)
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BX_DEBUG(("read PCI register 0x%02x value 0x%04x", address, value));
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else if (io_len == 4)
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BX_DEBUG(("read PCI register 0x%02x value 0x%08x", address, value));
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return value;
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}
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// pci configuration space write callback handler
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void bx_pcipnic_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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{
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Bit8u value8, oldval;
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bx_bool baseaddr_change = 0;
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bx_bool romaddr_change = 0;
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if (((address >= 0x10) && (address < 0x20)) ||
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((address > 0x23) && (address < 0x30)))
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return;
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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oldval = BX_PNIC_THIS pci_conf[address+i];
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switch (address+i) {
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case 0x04:
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value8 &= 0x01;
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break;
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case 0x3c:
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if (value8 != oldval) {
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BX_INFO(("new irq line = %d", value8));
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}
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break;
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case 0x20:
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value8 = (value8 & 0xfc) | 0x01;
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case 0x21:
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case 0x22:
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case 0x23:
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baseaddr_change = (value8 != oldval);
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break;
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case 0x30:
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case 0x31:
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case 0x32:
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case 0x33:
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if (BX_PNIC_THIS pci_rom_size > 0) {
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if ((address+i) == 0x30) {
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value8 &= 0x01;
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} else if ((address+i) == 0x31) {
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value8 &= 0xfc;
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}
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romaddr_change = 1;
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break;
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}
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default:
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value8 = oldval;
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}
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BX_PNIC_THIS pci_conf[address+i] = value8;
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}
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if (baseaddr_change) {
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if (DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
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&BX_PNIC_THIS pci_base_address[4],
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&BX_PNIC_THIS pci_conf[0x20],
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16, &pnic_iomask[0], "PNIC")) {
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BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS pci_base_address[4]));
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}
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}
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if (romaddr_change) {
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if (DEV_pci_set_base_mem(BX_PNIC_THIS_PTR, mem_read_handler,
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mem_write_handler,
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&BX_PNIC_THIS pci_rom_address,
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&BX_PNIC_THIS pci_conf[0x30],
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BX_PNIC_THIS pci_rom_size)) {
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BX_INFO(("new ROM address: 0x%08x", BX_PNIC_THIS pci_rom_address));
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}
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}
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if (io_len == 1)
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BX_DEBUG(("write PCI register 0x%02x value 0x%02x", address, value));
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else if (io_len == 2)
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BX_DEBUG(("write PCI register 0x%02x value 0x%04x", address, value));
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else if (io_len == 4)
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BX_DEBUG(("write PCI register 0x%02x value 0x%08x", address, value));
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}
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/*
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* Execute a hardware command.
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*/
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void bx_pcipnic_c::exec_command(void)
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{
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Bit16u command = BX_PNIC_THIS s.rCmd;
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Bit16u ilength = BX_PNIC_THIS s.rLength;
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Bit8u *data = BX_PNIC_THIS s.rData;
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// Default return values
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Bit16u status = PNIC_STATUS_UNKNOWN_CMD;
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Bit16u olength = 0;
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if (ilength != BX_PNIC_THIS s.rDataCursor)
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BX_PANIC(("PNIC command issued with incomplete data (should be %u, is %u)",
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ilength, BX_PNIC_THIS s.rDataCursor));
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switch (command) {
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case PNIC_CMD_NOOP:
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status = PNIC_STATUS_OK;
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break;
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case PNIC_CMD_API_VER:
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Bit16u api_version;
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api_version = PNIC_API_VERSION;
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olength = sizeof(api_version);
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memcpy (data, &api_version, sizeof(api_version));
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status = PNIC_STATUS_OK;
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break;
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case PNIC_CMD_READ_MAC:
|
|
olength = sizeof (BX_PNIC_THIS s.macaddr);
|
|
memcpy (data, BX_PNIC_THIS s.macaddr, olength);
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
case PNIC_CMD_RESET:
|
|
/* Flush the receive queue */
|
|
BX_PNIC_THIS s.recvQueueLength = 0;
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
case PNIC_CMD_XMIT:
|
|
BX_PNIC_THIS ethdev->sendpkt(data, ilength);
|
|
if (BX_PNIC_THIS s.irqEnabled) {
|
|
set_irq_level(1);
|
|
}
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
case PNIC_CMD_RECV:
|
|
if (BX_PNIC_THIS s.recvQueueLength > 0) {
|
|
int idx = (BX_PNIC_THIS s.recvIndex - BX_PNIC_THIS s.recvQueueLength
|
|
+ PNIC_RECV_RINGS) % PNIC_RECV_RINGS;
|
|
olength = BX_PNIC_THIS s.recvRingLength[idx];
|
|
memcpy (data, BX_PNIC_THIS s.recvRing[idx], olength);
|
|
BX_PNIC_THIS s.recvQueueLength--;
|
|
}
|
|
if (! BX_PNIC_THIS s.recvQueueLength) {
|
|
set_irq_level(0);
|
|
}
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
case PNIC_CMD_RECV_QLEN:
|
|
Bit16u qlen;
|
|
|
|
qlen = BX_PNIC_THIS s.recvQueueLength;
|
|
olength = sizeof(qlen);
|
|
memcpy (data, &qlen, sizeof(qlen));
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
case PNIC_CMD_MASK_IRQ:
|
|
Bit8u enabled;
|
|
|
|
enabled = *((Bit8u*)data);
|
|
BX_PNIC_THIS s.irqEnabled = enabled;
|
|
if (enabled && BX_PNIC_THIS s.recvQueueLength) {
|
|
set_irq_level(1);
|
|
} else {
|
|
set_irq_level(0);
|
|
}
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
case PNIC_CMD_FORCE_IRQ:
|
|
set_irq_level(1);
|
|
status = PNIC_STATUS_OK;
|
|
break;
|
|
|
|
default:
|
|
BX_ERROR(("Unknown PNIC command %x (data length %u)", command, ilength));
|
|
status = PNIC_STATUS_UNKNOWN_CMD;
|
|
break;
|
|
}
|
|
|
|
// Set registers
|
|
BX_PNIC_THIS s.rStatus = status;
|
|
BX_PNIC_THIS s.rLength = olength;
|
|
BX_PNIC_THIS s.rDataCursor = 0;
|
|
}
|
|
|
|
/*
|
|
* Callback from the eth system driver to check if the device can receive
|
|
*/
|
|
Bit32u bx_pcipnic_c::rx_status_handler(void *arg)
|
|
{
|
|
bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) arg;
|
|
return class_ptr->rx_status();
|
|
}
|
|
|
|
Bit32u bx_pcipnic_c::rx_status()
|
|
{
|
|
Bit32u status = BX_NETDEV_100MBIT;
|
|
if (BX_PNIC_THIS s.recvQueueLength < PNIC_RECV_RINGS) {
|
|
status |= BX_NETDEV_RXREADY;
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Callback from the eth system driver when a frame has arrived
|
|
*/
|
|
void bx_pcipnic_c::rx_handler(void *arg, const void *buf, unsigned len)
|
|
{
|
|
// BX_DEBUG(("rx_handler with length %d", len));
|
|
bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) arg;
|
|
class_ptr->rx_frame(buf, len);
|
|
}
|
|
|
|
/*
|
|
* rx_frame() - called by the platform-specific code when an
|
|
* ethernet frame has been received. The destination address
|
|
* is tested to see if it should be accepted, and if the
|
|
* rx ring has enough room, it is copied into it and
|
|
* the receive process is updated
|
|
*/
|
|
void bx_pcipnic_c::rx_frame(const void *buf, unsigned io_len)
|
|
{
|
|
// Check packet length
|
|
if (io_len > PNIC_DATA_SIZE) {
|
|
BX_PANIC(("PNIC receive: data size %u exceeded buffer size %u",
|
|
io_len, PNIC_DATA_SIZE));
|
|
// Truncate if user continues
|
|
io_len = PNIC_DATA_SIZE;
|
|
}
|
|
// Check receive ring is not full
|
|
if (BX_PNIC_THIS s.recvQueueLength == PNIC_RECV_RINGS) {
|
|
BX_ERROR(("PNIC receive: receive ring full, discarding packet"));
|
|
return;
|
|
}
|
|
// Copy data to receive ring and record length
|
|
memcpy (BX_PNIC_THIS s.recvRing[BX_PNIC_THIS s.recvIndex], buf, io_len);
|
|
BX_PNIC_THIS s.recvRingLength[BX_PNIC_THIS s.recvIndex] = io_len;
|
|
// Move to next ring entry
|
|
BX_PNIC_THIS s.recvIndex = (BX_PNIC_THIS s.recvIndex + 1) % PNIC_RECV_RINGS;
|
|
BX_PNIC_THIS s.recvQueueLength++;
|
|
|
|
// Generate interrupt if enabled
|
|
if (BX_PNIC_THIS s.irqEnabled) {
|
|
set_irq_level(1);
|
|
}
|
|
}
|
|
|
|
#endif // BX_SUPPORT_PCI && BX_SUPPORT_PCIPNIC
|