771 lines
25 KiB
C++
771 lines
25 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: segment_ctrl_pro.cc,v 1.76 2007-11-24 14:22:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
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{
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if (protected_mode())
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{
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS])
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{
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bx_selector_t ss_selector;
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bx_descriptor_t descriptor;
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Bit32u dword1, dword2;
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parse_selector(new_value, &ss_selector);
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if ((new_value & 0xfffc) == 0) { /* null selector */
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#if BX_SUPPORT_X86_64
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// allow SS = 0 in 64 bit mode only with cpl != 3 and rpl=cpl
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if (Is64BitMode() && CPL != 3 && ss_selector.rpl == CPL) {
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seg->selector.index = 0;
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seg->selector.ti = 0;
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seg->selector.rpl = 0;
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seg->selector.value = 0;
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seg->cache.valid = 0; /* invalidate null selector */
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return;
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}
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#endif
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BX_ERROR(("load_seg_reg(SS): loading null selector"));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
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/* selector's RPL must = CPL, else #GP(selector) */
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if (ss_selector.rpl != CPL) {
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BX_ERROR(("load_seg_reg(SS): rpl != CPL"));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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parse_descriptor(dword1, dword2, &descriptor);
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if (descriptor.valid==0) {
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BX_ERROR(("load_seg_reg(SS): valid bit cleared"));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* AR byte must indicate a writable data segment else #GP(selector) */
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if (descriptor.segment==0 || IS_CODE_SEGMENT(descriptor.type) ||
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IS_DATA_SEGMENT_WRITEABLE(descriptor.type) == 0)
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{
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BX_ERROR(("load_seg_reg(SS): not writable data segment"));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* DPL in the AR byte must equal CPL else #GP(selector) */
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if (descriptor.dpl != CPL) {
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BX_ERROR(("load_seg_reg(SS): dpl != CPL"));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* segment must be marked PRESENT else #SS(selector) */
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if (! IS_PRESENT(descriptor)) {
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BX_ERROR(("load_seg_reg(SS): not present"));
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exception(BX_SS_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* load SS with selector, load SS cache with descriptor */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector = ss_selector;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache = descriptor;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
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/* now set accessed bit in descriptor */
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dword2 |= 0x0100;
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if (ss_selector.ti == 0) { /* GDT */
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access_linear(BX_CPU_THIS_PTR gdtr.base + ss_selector.index*8 + 4, 4, 0,
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BX_WRITE, &dword2);
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}
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else { /* LDT */
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access_linear(BX_CPU_THIS_PTR ldtr.cache.u.system.base + ss_selector.index*8 + 4, 4, 0,
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BX_WRITE, &dword2);
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}
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return;
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}
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else if ( (seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS]) ||
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(seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES])
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#if BX_CPU_LEVEL >= 3
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|| (seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS]) ||
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(seg==&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS])
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#endif
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)
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{
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bx_descriptor_t descriptor;
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bx_selector_t selector;
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Bit32u dword1, dword2;
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if ((new_value & 0xfffc) == 0) { /* null selector */
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seg->selector.index = 0;
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seg->selector.ti = 0;
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seg->selector.rpl = 0;
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seg->selector.value = 0;
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seg->cache.valid = 0; /* invalidate null selector */
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return;
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}
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parse_selector(new_value, &selector);
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fetch_raw_descriptor(&selector, &dword1, &dword2, BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &descriptor);
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if (descriptor.valid==0) {
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BX_ERROR(("load_seg_reg(%s): valid bit cleared", strseg(seg)));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* AR byte must indicate data or readable code segment else #GP(selector) */
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if (descriptor.segment==0 || (IS_CODE_SEGMENT(descriptor.type) &&
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IS_CODE_SEGMENT_READABLE(descriptor.type) == 0))
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{
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BX_ERROR(("load_seg_reg(%s): not data or readable code", strseg(seg)));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* If data or non-conforming code, then both the RPL and the CPL
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* must be less than or equal to DPL in AR byte else #GP(selector) */
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if (IS_DATA_SEGMENT(descriptor.type) ||
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IS_CODE_SEGMENT_NON_CONFORMING(descriptor.type))
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{
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if ((selector.rpl > descriptor.dpl) || (CPL > descriptor.dpl)) {
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BX_ERROR(("load_seg_reg(%s): RPL & CPL must be <= DPL", strseg(seg)));
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exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
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}
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}
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/* segment must be marked PRESENT else #NP(selector) */
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if (! IS_PRESENT(descriptor)) {
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BX_ERROR(("load_seg_reg(%s): segment not present", strseg(seg)));
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exception(BX_NP_EXCEPTION, new_value & 0xfffc, 0);
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}
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/* load segment register with selector */
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/* load segment register-cache with descriptor */
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seg->selector = selector;
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seg->cache = descriptor;
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seg->cache.valid = 1;
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/* now set accessed bit in descriptor */
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/* wmr: don't bother if it's already set (thus allowing */
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/* GDT to be in read-only pages like real hdwe does) */
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if (!(dword2 & 0x0100)) {
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dword2 |= 0x0100;
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if (selector.ti == 0) { /* GDT */
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access_linear(BX_CPU_THIS_PTR gdtr.base + selector.index*8 + 4, 4, 0,
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BX_WRITE, &dword2);
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}
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else { /* LDT */
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access_linear(BX_CPU_THIS_PTR ldtr.cache.u.system.base + selector.index*8 + 4, 4, 0,
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BX_WRITE, &dword2);
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}
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}
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return;
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}
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else {
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BX_PANIC(("load_seg_reg(): invalid segment register passed!"));
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return;
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}
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}
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/* real or v8086 mode */
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/* www.x86.org:
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According to Intel, each time any segment register is loaded in real
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mode, the base address is calculated as 16 times the segment value,
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while the access rights and size limit attributes are given fixed,
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"real-mode compatible" values. This is not true. In fact, only the CS
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descriptor caches for the 286, 386, and 486 get loaded with fixed
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values each time the segment register is loaded. Loading CS, or any
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other segment register in real mode, on later Intel processors doesn't
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change the access rights or the segment size limit attributes stored
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in the descriptor cache registers. For these segments, the access
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rights and segment size limit attributes from any previous setting are
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honored. */
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seg->selector.value = new_value;
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seg->selector.rpl = real_mode() ? 0 : 3;
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seg->cache.valid = 1;
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seg->cache.u.segment.base = new_value << 4;
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seg->cache.segment = 1; /* regular segment */
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seg->cache.p = 1; /* present */
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
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seg->cache.type = BX_CODE_EXEC_READ_ACCESSED;
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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handleAlignmentCheck(); // CPL was modified
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#endif
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invalidate_prefetch_q();
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}
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else {
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seg->cache.type = BX_DATA_READ_WRITE_ACCESSED;
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}
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/* Do not modify segment limit and AR bytes when in real mode */
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if (real_mode()) return;
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seg->cache.dpl = 3; /* we are in v8086 mode */
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seg->cache.u.segment.limit = 0xffff;
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seg->cache.u.segment.limit_scaled = 0xffff;
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#if BX_CPU_LEVEL >= 3
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seg->cache.u.segment.g = 0; /* byte granular */
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seg->cache.u.segment.d_b = 0; /* default 16bit size */
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#if BX_SUPPORT_X86_64
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seg->cache.u.segment.l = 0; /* default 16bit size */
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#endif
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seg->cache.u.segment.avl = 0;
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#endif
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}
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::loadSRegLMNominal(unsigned segI, unsigned selector, unsigned dpl)
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{
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bx_segment_reg_t *seg = & BX_CPU_THIS_PTR sregs[segI];
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// Load a segment register in long-mode with nominal values,
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// so descriptor cache values are compatible with existing checks.
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seg->cache.u.segment.base = 0;
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// I doubt we need limit_scaled. If we do, it should be
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// of type bx_addr and be maxed to 64bits, not 32.
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seg->cache.u.segment.limit_scaled = 0xffffffff;
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seg->cache.valid = 1;
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seg->cache.dpl = dpl;
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seg->selector.value = selector;
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}
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#endif
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void BX_CPU_C::validate_seg_reg(unsigned seg)
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{
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/*
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FOR (seg = ES, DS, FS, GS)
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DO
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IF ((seg.attr.dpl < CPL) && ((seg.attr.type = 'data')
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|| (seg.attr.type = 'non-conforming-code')))
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{
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seg = NULL // can't use lower dpl data segment at higher cpl
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}
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END
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*/
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bx_segment_reg_t *segment = &BX_CPU_THIS_PTR sregs[seg];
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if (segment->cache.dpl < CPL)
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{
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// invalidate if data or non-conforming code segment
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if (segment->cache.valid==0 || segment->cache.segment==0 ||
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IS_DATA_SEGMENT(segment->cache.type) ||
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IS_CODE_SEGMENT_NON_CONFORMING(segment->cache.type))
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{
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segment->selector.value = 0;
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segment->cache.valid = 0;
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}
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}
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}
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void BX_CPU_C::validate_seg_regs(void)
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{
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validate_seg_reg(BX_SEG_REG_ES);
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validate_seg_reg(BX_SEG_REG_DS);
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validate_seg_reg(BX_SEG_REG_FS);
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validate_seg_reg(BX_SEG_REG_GS);
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}
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#if BX_CPU_LEVEL >= 2
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::parse_selector(Bit16u raw_selector, bx_selector_t *selector)
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{
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selector->value = raw_selector;
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selector->index = raw_selector >> 3;
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selector->ti = (raw_selector >> 2) & 0x01;
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selector->rpl = raw_selector & 0x03;
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}
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#endif
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Bit8u BX_CPP_AttrRegparmN(1)
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BX_CPU_C::ar_byte(const bx_descriptor_t *d)
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{
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if (d->valid == 0) {
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return(0);
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}
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return (d->type) |
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(d->segment << 4) |
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(d->dpl << 5) |
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(d->p << 7);
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}
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::set_ar_byte(bx_descriptor_t *d, Bit8u ar_byte)
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{
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d->p = (ar_byte >> 7) & 0x01;
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d->dpl = (ar_byte >> 5) & 0x03;
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d->segment = (ar_byte >> 4) & 0x01;
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d->type = (ar_byte & 0x0f);
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}
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Bit32u BX_CPP_AttrRegparmN(1)
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BX_CPU_C::get_descriptor_l(const bx_descriptor_t *d)
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{
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Bit32u val;
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if (d->valid == 0) {
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return(0);
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}
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if (d->segment) {
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val = ((d->u.segment.base & 0xffff) << 16) | (d->u.segment.limit & 0xffff);
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return(val);
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}
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else {
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switch (d->type) {
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case 0: // Reserved (not defined)
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BX_ERROR(("#get_descriptor_l(): type %d not finished", d->type));
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return(0);
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case BX_SYS_SEGMENT_LDT:
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case BX_SYS_SEGMENT_AVAIL_286_TSS:
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case BX_SYS_SEGMENT_BUSY_286_TSS:
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case BX_SYS_SEGMENT_AVAIL_386_TSS:
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case BX_SYS_SEGMENT_BUSY_386_TSS:
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val = ((d->u.system.base & 0xffff) << 16) | (d->u.system.limit & 0xffff);
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return(val);
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default:
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BX_PANIC(("#get_descriptor_l(): type %d not finished", d->type));
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return(0);
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}
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}
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}
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Bit32u BX_CPP_AttrRegparmN(1)
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BX_CPU_C::get_descriptor_h(const bx_descriptor_t *d)
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{
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Bit32u val;
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if (d->valid == 0) {
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return(0);
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}
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if (d->segment) {
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val = (d->u.segment.base & 0xff000000) |
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((d->u.segment.base >> 16) & 0x000000ff) |
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(d->type << 8) |
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(d->segment << 12) |
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(d->dpl << 13) |
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(d->p << 15) |
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(d->u.segment.limit & 0xf0000) |
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(d->u.segment.avl << 20) |
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#if BX_SUPPORT_X86_64
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(d->u.segment.l << 21) |
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#endif
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(d->u.segment.d_b << 22) |
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(d->u.segment.g << 23);
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return(val);
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}
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else {
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switch (d->type) {
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case 0: // Reserved (not yet defined)
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BX_ERROR(("#get_descriptor_h(): type %d not finished", d->type));
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return(0);
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case BX_SYS_SEGMENT_AVAIL_286_TSS:
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case BX_SYS_SEGMENT_BUSY_286_TSS:
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BX_ASSERT(d->u.system.g == 0);
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BX_ASSERT(d->u.system.avl == 0);
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// fall through
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case BX_SYS_SEGMENT_LDT:
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case BX_SYS_SEGMENT_AVAIL_386_TSS:
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case BX_SYS_SEGMENT_BUSY_386_TSS:
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val = ((d->u.system.base >> 16) & 0xff) |
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(d->type << 8) |
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(d->dpl << 13) |
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(d->p << 15) |
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(d->u.system.limit & 0xf0000) |
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(d->u.system.avl << 20) |
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(d->u.system.g << 23) |
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(d->u.system.base & 0xff000000);
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return(val);
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default:
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BX_PANIC(("#get_descriptor_h(): type %d not finished", d->type));
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return(0);
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}
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}
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}
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#if BX_CPU_LEVEL >= 3
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Bit16u BX_CPP_AttrRegparmN(1)
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BX_CPU_C::get_segment_ar_data(const bx_descriptor_t *d) // used for SMM
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{
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Bit16u val = 0;
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if (d->segment) { /* data/code segment descriptors */
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val = (d->type) |
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(d->segment << 4) |
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(d->dpl << 5) |
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(d->p << 7) |
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(d->u.segment.avl << 12) |
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#if BX_SUPPORT_X86_64
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(d->u.segment.l << 13) |
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#endif
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(d->u.segment.d_b << 14) |
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(d->u.segment.g << 15);
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return(val);
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}
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switch (d->type) {
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case BX_SYS_SEGMENT_AVAIL_286_TSS:
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case BX_SYS_SEGMENT_BUSY_286_TSS:
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BX_ASSERT(d->u.system.g == 0);
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BX_ASSERT(d->u.system.avl == 0);
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// fall through
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case BX_SYS_SEGMENT_LDT:
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case BX_SYS_SEGMENT_AVAIL_386_TSS:
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case BX_SYS_SEGMENT_BUSY_386_TSS:
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val = (d->type) |
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(d->dpl << 5) |
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(d->p << 7) |
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(d->u.system.avl << 12) |
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(d->u.system.g << 15);
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return(val);
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default:
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BX_PANIC(("get_segment_ar_data(): case %u unsupported", (unsigned) d->type));
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}
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return val;
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}
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bx_bool BX_CPU_C::set_segment_ar_data(bx_segment_reg_t *seg,
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Bit16u raw_selector, bx_address base, Bit32u limit, Bit16u ar_data)
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{
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parse_selector(raw_selector, &seg->selector);
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|
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bx_descriptor_t *d = &seg->cache;
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|
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d->p = (ar_data >> 7) & 0x01;
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d->dpl = (ar_data >> 5) & 0x03;
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d->segment = (ar_data >> 4) & 0x01;
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d->type = (ar_data & 0x0f);
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|
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if (d->segment) { /* data/code segment descriptors */
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d->u.segment.g = (ar_data >> 15) & 0x01;
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d->u.segment.d_b = (ar_data >> 14) & 0x01;
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#if BX_SUPPORT_X86_64
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d->u.segment.l = (ar_data >> 13) & 0x01;
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#endif
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d->u.segment.avl = (ar_data >> 12) & 0x01;
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d->u.segment.base = base;
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d->u.segment.limit = limit;
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if (d->u.segment.g) {
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if (IS_DATA_SEGMENT(d->type) && IS_DATA_SEGMENT_EXPAND_DOWN(d->type))
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d->u.segment.limit_scaled = (d->u.segment.limit << 12);
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else
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d->u.segment.limit_scaled = (d->u.segment.limit << 12) | 0x0fff;
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}
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else
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d->u.segment.limit_scaled = d->u.segment.limit;
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d->valid = 1;
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}
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else {
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switch(d->type) {
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case BX_SYS_SEGMENT_LDT:
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case BX_SYS_SEGMENT_AVAIL_286_TSS:
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case BX_SYS_SEGMENT_BUSY_286_TSS:
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case BX_SYS_SEGMENT_AVAIL_386_TSS:
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case BX_SYS_SEGMENT_BUSY_386_TSS:
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d->valid = 1;
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d->u.system.avl = (ar_data >> 12) & 0x01;
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d->u.system.g = (ar_data >> 15) & 0x01;
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d->u.system.base = base;
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d->u.system.limit = limit;
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if (d->u.system.g)
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d->u.system.limit_scaled = (d->u.system.limit << 12) | 0x0fff;
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else
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d->u.system.limit_scaled = (d->u.system.limit);
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break;
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default:
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BX_PANIC(("set_segment_ar_data(): case %u unsupported", (unsigned) d->type));
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}
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}
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/* invalidate if null selector */
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if ((raw_selector & 0xfffc) == 0) {
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seg->cache.valid = 0;
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}
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return seg->cache.valid;
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}
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#endif
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
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{
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Bit8u AR_byte;
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AR_byte = dword2 >> 8;
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temp->p = (AR_byte >> 7) & 0x01;
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temp->dpl = (AR_byte >> 5) & 0x03;
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temp->segment = (AR_byte >> 4) & 0x01;
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temp->type = (AR_byte & 0x0f);
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temp->valid = 0; /* start out invalid */
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if (temp->segment) { /* data/code segment descriptors */
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temp->u.segment.limit = (dword1 & 0xffff);
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temp->u.segment.base = (dword1 >> 16) | ((dword2 & 0xFF) << 16);
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#if BX_CPU_LEVEL >= 3
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temp->u.segment.limit |= (dword2 & 0x000F0000);
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temp->u.segment.g = (dword2 & 0x00800000) > 0;
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temp->u.segment.d_b = (dword2 & 0x00400000) > 0;
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#if BX_SUPPORT_X86_64
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temp->u.segment.l = (dword2 & 0x00200000) > 0;
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#endif
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temp->u.segment.avl = (dword2 & 0x00100000) > 0;
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temp->u.segment.base |= (dword2 & 0xFF000000);
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|
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if (temp->u.segment.g) {
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if (IS_DATA_SEGMENT(temp->type) && IS_DATA_SEGMENT_EXPAND_DOWN(temp->type))
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temp->u.segment.limit_scaled = (temp->u.segment.limit << 12);
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else
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temp->u.segment.limit_scaled = (temp->u.segment.limit << 12) | 0x0fff;
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}
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else
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#endif
|
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temp->u.segment.limit_scaled = temp->u.segment.limit;
|
|
|
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temp->valid = 1;
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|
}
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else { // system & gate segment descriptors
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switch (temp->type) {
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case 0: // reserved
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case 8: // reserved
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case 10: // reserved
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case 13: // reserved
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temp->valid = 0;
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break;
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|
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case BX_SYS_SEGMENT_AVAIL_286_TSS:
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case BX_SYS_SEGMENT_BUSY_286_TSS:
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|
temp->u.system.base = (dword1 >> 16) | ((dword2 & 0xff) << 16);
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|
temp->u.system.limit = (dword1 & 0xffff);
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temp->u.system.limit_scaled = temp->u.system.limit;
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|
temp->u.system.g = 0;
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temp->u.system.avl = 0;
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temp->valid = 1;
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break;
|
|
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case BX_286_CALL_GATE:
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case BX_286_INTERRUPT_GATE:
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|
case BX_286_TRAP_GATE:
|
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// param count only used for call gate
|
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temp->u.gate.param_count = dword2 & 0x1f;
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temp->u.gate.dest_selector = dword1 >> 16;
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temp->u.gate.dest_offset = dword1 & 0xffff;
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|
temp->valid = 1;
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|
break;
|
|
|
|
case BX_386_CALL_GATE:
|
|
case BX_386_INTERRUPT_GATE:
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|
case BX_386_TRAP_GATE:
|
|
// param count only used for call gate
|
|
temp->u.gate.param_count = dword2 & 0x1f;
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|
temp->u.gate.dest_selector = dword1 >> 16;
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temp->u.gate.dest_offset = (dword2 & 0xffff0000) |
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(dword1 & 0x0000ffff);
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|
temp->valid = 1;
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|
break;
|
|
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|
case BX_TASK_GATE:
|
|
temp->u.taskgate.tss_selector = dword1 >> 16;
|
|
temp->valid = 1;
|
|
break;
|
|
|
|
case BX_SYS_SEGMENT_LDT:
|
|
case BX_SYS_SEGMENT_AVAIL_386_TSS:
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|
case BX_SYS_SEGMENT_BUSY_386_TSS:
|
|
temp->u.system.base = (dword1 >> 16) |
|
|
((dword2 & 0xff) << 16) | (dword2 & 0xff000000);
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|
temp->u.system.limit = (dword1 & 0x0000ffff) | (dword2 & 0x000f0000);
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|
temp->u.system.g = (dword2 & 0x00800000) > 0;
|
|
temp->u.system.avl = (dword2 & 0x00100000) > 0;
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|
if (temp->u.system.g)
|
|
temp->u.system.limit_scaled = (temp->u.system.limit << 12) | 0x0fff;
|
|
else
|
|
temp->u.system.limit_scaled = (temp->u.system.limit);
|
|
temp->valid = 1;
|
|
break;
|
|
|
|
default:
|
|
BX_PANIC(("parse_descriptor(): case %u unfinished", (unsigned) temp->type));
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|
temp->valid = 0;
|
|
}
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|
}
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|
}
|
|
|
|
void BX_CPP_AttrRegparmN(3)
|
|
BX_CPU_C::load_ss(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cpl)
|
|
{
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector = *selector;
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|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache = *descriptor;
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|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = cpl;
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|
|
|
// Add cpl to the selector value.
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|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value =
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|
(0xfffc & BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value) | cpl;
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
|
loadSRegLMNominal(BX_SEG_REG_SS, selector->value, cpl);
|
|
return;
|
|
}
|
|
#endif
|
|
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value & 0xfffc) == 0)
|
|
BX_PANIC(("load_ss(): null selector passed"));
|
|
|
|
if (!BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid) {
|
|
BX_PANIC(("load_ss(): invalid selector/descriptor passed."));
|
|
}
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 2
|
|
void BX_CPP_AttrRegparmN(3)
|
|
BX_CPU_C::fetch_raw_descriptor(const bx_selector_t *selector,
|
|
Bit32u *dword1, Bit32u *dword2, unsigned exception_no)
|
|
{
|
|
Bit32u index = selector->index;
|
|
|
|
if (selector->ti == 0) { /* GDT */
|
|
if ((index*8 + 7) > BX_CPU_THIS_PTR gdtr.limit) {
|
|
BX_ERROR(("fetch_raw_descriptor: GDT: index (%x)%x > limit (%x)",
|
|
index*8 + 7, index, BX_CPU_THIS_PTR gdtr.limit));
|
|
exception(exception_no, selector->value & 0xfffc, 0);
|
|
}
|
|
bx_address offset = BX_CPU_THIS_PTR gdtr.base + index*8;
|
|
access_linear(offset, 4, 0, BX_READ, dword1);
|
|
access_linear(offset + 4, 4, 0, BX_READ, dword2);
|
|
}
|
|
else { /* LDT */
|
|
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
|
|
BX_PANIC(("fetch_raw_descriptor: LDTR.valid=0"));
|
|
debug(BX_CPU_THIS_PTR prev_rip);
|
|
}
|
|
if ((index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled) {
|
|
BX_ERROR(("fetch_raw_descriptor: LDT: index (%x)%x > limit (%x)",
|
|
index*8 + 7, index, BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled));
|
|
exception(exception_no, selector->value & 0xfffc, 0);
|
|
}
|
|
bx_address offset = BX_CPU_THIS_PTR ldtr.cache.u.system.base + index*8;
|
|
access_linear(offset, 4, 0, BX_READ, dword1);
|
|
access_linear(offset + 4, 4, 0, BX_READ, dword2);
|
|
}
|
|
}
|
|
|
|
bx_bool BX_CPP_AttrRegparmN(3)
|
|
BX_CPU_C::fetch_raw_descriptor2(const bx_selector_t *selector, Bit32u *dword1, Bit32u *dword2)
|
|
{
|
|
Bit32u index = selector->index;
|
|
|
|
if (selector->ti == 0) { /* GDT */
|
|
if ((index*8 + 7) > BX_CPU_THIS_PTR gdtr.limit)
|
|
return(0);
|
|
bx_address offset = BX_CPU_THIS_PTR gdtr.base + index*8;
|
|
access_linear(offset, 4, 0, BX_READ, dword1);
|
|
access_linear(offset + 4, 4, 0, BX_READ, dword2);
|
|
return(1);
|
|
}
|
|
else { /* LDT */
|
|
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
|
|
BX_PANIC(("fetch_raw_descriptor2: LDTR.valid=0"));
|
|
return(0);
|
|
}
|
|
if ((index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled)
|
|
return(0);
|
|
bx_address offset = BX_CPU_THIS_PTR ldtr.cache.u.system.base + index*8;
|
|
access_linear(offset, 4, 0, BX_READ, dword1);
|
|
access_linear(offset + 4, 4, 0, BX_READ, dword2);
|
|
return(1);
|
|
}
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
void BX_CPU_C::fetch_raw_descriptor64(const bx_selector_t *selector,
|
|
Bit32u *dword1, Bit32u *dword2, Bit32u *dword3, unsigned exception_no)
|
|
{
|
|
Bit32u index = selector->index;
|
|
Bit32u dword4;
|
|
|
|
if (selector->ti == 0) { /* GDT */
|
|
if ((index*8 + 15) > BX_CPU_THIS_PTR gdtr.limit) {
|
|
BX_ERROR(("fetch_raw_descriptor64: GDT: index (%x)%x > limit (%x)",
|
|
index*8 + 15, index, BX_CPU_THIS_PTR gdtr.limit));
|
|
exception(exception_no, selector->value & 0xfffc, 0);
|
|
}
|
|
bx_address offset = BX_CPU_THIS_PTR gdtr.base + index*8;
|
|
access_linear(offset, 4, 0, BX_READ, dword1);
|
|
access_linear(offset + 4, 4, 0, BX_READ, dword2);
|
|
access_linear(offset + 8, 4, 0, BX_READ, dword3);
|
|
access_linear(offset + 12, 4, 0, BX_READ, &dword4);
|
|
}
|
|
else { /* LDT */
|
|
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
|
|
BX_PANIC(("fetch_raw_descriptor: LDTR.valid=0"));
|
|
debug(BX_CPU_THIS_PTR prev_rip);
|
|
}
|
|
if ((index*8 + 15) > BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled) {
|
|
BX_ERROR(("fetch_raw_descriptor64: LDT: index (%x)%x > limit (%x)",
|
|
index*8 + 15, index, BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled));
|
|
exception(exception_no, selector->value & 0xfffc, 0);
|
|
}
|
|
bx_address offset = BX_CPU_THIS_PTR ldtr.cache.u.system.base + index*8;
|
|
access_linear(offset, 4, 0, BX_READ, dword1);
|
|
access_linear(offset + 4, 4, 0, BX_READ, dword2);
|
|
access_linear(offset + 8, 4, 0, BX_READ, dword3);
|
|
access_linear(offset + 12, 4, 0, BX_READ, &dword4);
|
|
}
|
|
|
|
if (dword4 != 0) {
|
|
BX_ERROR(("fetch_raw_descriptor64: extended attributes DWORD4 != 0"));
|
|
exception(BX_GP_EXCEPTION, selector->value & 0xfffc, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#endif
|