767fb77ebd
1. Should speed up the simulation (eliminate seg.limit check per every instruction exec) 2. Should help for DT (h.johansson request)
1054 lines
32 KiB
C++
1054 lines
32 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.150 2006-05-04 19:54:25 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#include "iodev/iodev.h"
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#if BX_EXTERNAL_DEBUGGER
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#include "extdb.h"
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#endif
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#if BX_PROVIDE_CPU_MEMORY==1
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#if BX_ADDRESS_SPACES==1
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BOCHSAPI BX_MEM_C bx_mem;
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#else
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BOCHSAPI BX_MEM_C bx_mem_array[BX_ADDRESS_SPACES];
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#endif
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#endif
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#if BX_SUPPORT_ICACHE
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bxPageWriteStampTable pageWriteStampTable;
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void purgeICaches(void)
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{
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#if BX_SUPPORT_SMP
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for (unsigned i=0; i<BX_SMP_PROCESSORS; i++)
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BX_CPU(i)->iCache.purgeICacheEntries();
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#else
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BX_CPU(0)->iCache.purgeICacheEntries();
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#endif
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pageWriteStampTable.resetWriteStamps();
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}
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void flushICaches(void)
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{
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#if BX_SUPPORT_SMP
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for (unsigned i=0; i<BX_SMP_PROCESSORS; i++)
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BX_CPU(i)->iCache.flushICacheEntries();
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#else
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BX_CPU(0)->iCache.flushICacheEntries();
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#endif
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pageWriteStampTable.resetWriteStamps();
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}
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#define InstrumentICACHE 0
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#if InstrumentICACHE
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static unsigned iCacheLookups=0;
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static unsigned iCacheMisses=0;
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#define InstrICache_StatsMask 0xffffff
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#define InstrICache_Stats() {\
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if ((iCacheLookups & InstrICache_StatsMask) == 0) { \
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BX_INFO(("ICACHE lookups: %u, misses: %u, hit rate = %6.2f%% ", \
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iCacheLookups, \
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iCacheMisses, \
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(iCacheLookups-iCacheMisses) * 100.0 / iCacheLookups)); \
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iCacheLookups = iCacheMisses = 0; \
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} \
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}
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#define InstrICache_Increment(v) (v)++
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#else
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#define InstrICache_Stats()
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#define InstrICache_Increment(v)
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#endif
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#endif
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// notes:
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// The CHECK_MAX_INSTRUCTIONS macro allows cpu_loop to execute a few
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// instructions and then return so that the other processors have a chance to
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// run. This is used only when simulating multiple processors.
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//
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// If maximum instructions have been executed, return. The zero-count
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// means run forever.
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#define CHECK_MAX_INSTRUCTIONS(count) \
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if (count > 0) { \
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count--; \
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if (count == 0) return; \
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}
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#if BX_SUPPORT_SMP
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# define BX_TICK1_IF_SINGLE_PROCESSOR()
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#else
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# define BX_TICK1_IF_SINGLE_PROCESSOR() BX_TICK1()
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#endif
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// Make code more tidy with a few macros.
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#if BX_SUPPORT_X86_64==0
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#define RIP EIP
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#define RSP ESP
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#endif
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BX_CPP_INLINE bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, bx_address eipBiased)
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{
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unsigned ret;
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bxInstruction_c *i = iStorage;
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#if BX_SUPPORT_ICACHE
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
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unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
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bxICacheEntry_c *cache_entry = &(BX_CPU_THIS_PTR iCache.entry[iCacheHash]);
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i = &(cache_entry->i);
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Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
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InstrICache_Increment(iCacheLookups);
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InstrICache_Stats();
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if ((cache_entry->pAddr == pAddr) &&
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(cache_entry->writeStamp == pageWriteStamp))
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{
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// iCache hit. Instruction is already decoded and stored in the
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// instruction cache.
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#if BX_INSTRUMENTATION
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// An instruction was found in the iCache.
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BX_INSTR_OPCODE(BX_CPU_ID, BX_CPU_THIS_PTR eipFetchPtr + eipBiased,
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i->ilen(), BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
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#endif
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}
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else
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#endif
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{
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// iCache miss. No validated instruction with matching fetch parameters
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// is in the iCache. Or we're not compiling iCache support in, in which
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// case we always have an iCache miss. :^)
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bx_address remainingInPage;
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remainingInPage = (BX_CPU_THIS_PTR eipPageWindowSize - eipBiased);
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unsigned maxFetch = 15;
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if (remainingInPage < 15) maxFetch = remainingInPage;
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Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
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#if BX_SUPPORT_ICACHE
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// The entry will be marked valid if fetchdecode will succeed
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cache_entry->writeStamp = ICacheWriteStampInvalid;
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InstrICache_Increment(iCacheMisses);
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#endif
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
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ret = fetchDecode64(fetchPtr, i, maxFetch);
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else
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#endif
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ret = fetchDecode(fetchPtr, i, maxFetch);
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if (ret==0) {
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#if BX_SUPPORT_ICACHE
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i = iStorage; // return iStorage and leave icache entry invalid
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#endif
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boundaryFetch(fetchPtr, remainingInPage, i);
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}
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else
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{
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#if BX_SUPPORT_ICACHE
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cache_entry->pAddr = pAddr;
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cache_entry->writeStamp = pageWriteStamp;
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#endif
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#if BX_INSTRUMENTATION
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// An instruction was either fetched, or found in the iCache.
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BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, i->ilen(),
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
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#endif
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}
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}
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return i;
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}
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void BX_CPU_C::cpu_loop(Bit32u max_instr_count)
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{
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bxInstruction_c iStorage BX_CPP_AlignN(32);
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR break_point = 0;
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#if BX_MAGIC_BREAKPOINT
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BX_CPU_THIS_PTR magic_break = 0;
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#endif
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BX_CPU_THIS_PTR stop_reason = STOP_NO_REASON;
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#endif
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if (setjmp(BX_CPU_THIS_PTR jmp_buf_env))
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{
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// only from exception function can we get here ...
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BX_INSTR_NEW_INSTRUCTION(BX_CPU_ID);
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#if BX_GDBSTUB
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if (bx_dbg.gdbstub_enabled) {
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return;
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}
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#endif
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}
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#if BX_DEBUGGER
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// If the exception() routine has encountered a nasty fault scenario,
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// the debugger may request that control is returned to it so that
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// the situation may be examined.
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if (bx_guard.special_unwind_stack) {
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printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
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return;
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}
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#endif
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// We get here either by a normal function call, or by a longjmp
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// back from an exception() call. In either case, commit the
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// new EIP/ESP, and set up other environmental fields. This code
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// mirrors similar code below, after the interrupt() call.
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BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
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BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
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BX_CPU_THIS_PTR EXT = 0;
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BX_CPU_THIS_PTR errorno = 0;
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while (1) {
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// First check on events which occurred for previous instructions
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// (traps) and ones which are asynchronous to the CPU
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// (hardware interrupts).
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if (BX_CPU_THIS_PTR async_event) {
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if (handleAsyncEvent()) {
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// If request to return to caller ASAP.
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return;
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}
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}
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#if BX_DEBUGGER
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{
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bx_address debug_eip = BX_CPU_THIS_PTR prev_eip;
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if (dbg_is_begin_instr_bpoint(
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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debug_eip,
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BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + debug_eip,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
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Is64BitMode()))
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{
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return;
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}
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}
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#endif // #if BX_DEBUGGER
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#if BX_EXTERNAL_DEBUGGER
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if (regs.debug_state != debug_run) {
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bx_external_debugger(BX_CPU_THIS);
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}
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#endif
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bx_address eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
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if (eipBiased >= BX_CPU_THIS_PTR eipPageWindowSize) {
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prefetch();
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eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
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}
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// fetch and decode next instruction
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bxInstruction_c *i = fetchInstruction(&iStorage, eipBiased);
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bx_address next_RIP = RIP + i->ilen();
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BxExecutePtr_tR resolveModRM = i->ResolveModrm; // Get as soon as possible for speculation
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BxExecutePtr_t execute = i->execute; // fetch as soon as possible for speculation
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if (resolveModRM)
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BX_CPU_CALL_METHODR(resolveModRM, (i));
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// An instruction will have been fetched using either the normal case,
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// or the boundary fetch (across pages), by this point.
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BX_INSTR_FETCH_DECODE_COMPLETED(BX_CPU_ID, i);
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#if BX_DISASM
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if (BX_CPU_THIS_PTR trace) {
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// print the instruction that is about to be executed
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#if BX_DEBUGGER
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bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
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#else
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debug_disasm_instruction(BX_CPU_THIS_PTR prev_eip);
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#endif
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}
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#endif
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// decoding instruction compeleted -> continue with execution
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
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if ( !(i->repUsedL() && i->repeatableL()) ) {
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// non repeating instruction
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RIP = next_RIP;
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BX_CPU_CALL_METHOD(execute, (i));
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BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
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BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
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BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
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BX_TICK1_IF_SINGLE_PROCESSOR();
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}
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else {
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repeat_loop:
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if (i->repeatableZFL()) {
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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if (RCX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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RCX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) goto repeat_done;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) goto repeat_done;
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if (RCX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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else
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#endif
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if (i->as32L()) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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ECX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) goto repeat_done;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) goto repeat_done;
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if (ECX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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else {
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if (CX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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CX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) goto repeat_done;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) goto repeat_done;
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if (CX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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}
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else { // normal repeat, no concern for ZF
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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if (RCX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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RCX --;
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}
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if (RCX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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else
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#endif
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if (i->as32L()) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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ECX --;
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}
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if (ECX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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else { // 16bit addrsize
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if (CX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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CX --;
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}
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if (CX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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}
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// shouldn't get here from above
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repeat_not_done:
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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BX_TICK1_IF_SINGLE_PROCESSOR();
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event) {
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invalidate_prefetch_q();
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goto debugger_check;
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}
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goto repeat_loop;
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#else /* if BX_DEBUGGER == 1 */
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invalidate_prefetch_q();
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goto debugger_check;
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#endif
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repeat_done:
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RIP = next_RIP;
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BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
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BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
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BX_TICK1_IF_SINGLE_PROCESSOR();
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}
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debugger_check:
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// inform instrumentation about new instruction
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BX_INSTR_NEW_INSTRUCTION(BX_CPU_ID);
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#if BX_DEBUGGER
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// Mode switch support is in dbg_is_begin_instr_bpoint
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// note instr generating exceptions never reach this point.
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// (mch) Read/write, time break point support
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if (BX_CPU_THIS_PTR break_point) {
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switch (BX_CPU_THIS_PTR break_point) {
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case BREAK_POINT_TIME:
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BX_INFO(("[" FMT_LL "d] Caught time breakpoint", bx_pc_system.time_ticks()));
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BX_CPU_THIS_PTR stop_reason = STOP_TIME_BREAK_POINT;
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return;
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case BREAK_POINT_READ:
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BX_INFO(("[" FMT_LL "d] Caught read watch point", bx_pc_system.time_ticks()));
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BX_CPU_THIS_PTR stop_reason = STOP_READ_WATCH_POINT;
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return;
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case BREAK_POINT_WRITE:
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BX_INFO(("[" FMT_LL "d] Caught write watch point", bx_pc_system.time_ticks()));
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BX_CPU_THIS_PTR stop_reason = STOP_WRITE_WATCH_POINT;
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return;
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default:
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BX_PANIC(("Weird break point condition"));
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}
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}
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#if BX_MAGIC_BREAKPOINT
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// (mch) Magic break point support
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if (BX_CPU_THIS_PTR magic_break) {
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if (bx_dbg.magic_break_enabled) {
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BX_DEBUG(("Stopped on MAGIC BREAKPOINT"));
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BX_CPU_THIS_PTR stop_reason = STOP_MAGIC_BREAK_POINT;
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return;
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}
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else {
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BX_CPU_THIS_PTR magic_break = 0;
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BX_CPU_THIS_PTR stop_reason = STOP_NO_REASON;
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BX_DEBUG(("Ignoring MAGIC BREAKPOINT"));
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}
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}
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#endif
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{
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// check for icount or control-C. If found, set guard reg and return.
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bx_address debug_eip = BX_CPU_THIS_PTR prev_eip;
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if (dbg_is_end_instr_bpoint(
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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debug_eip,
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BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + debug_eip,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
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Is64BitMode()))
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{
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return;
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}
|
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}
|
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#endif // #if BX_DEBUGGER
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|
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#if BX_GDBSTUB
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if (bx_dbg.gdbstub_enabled) {
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unsigned int reason = bx_gdbstub_check(EIP);
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if (reason != GDBSTUB_STOP_NO_REASON) {
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return;
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}
|
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}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_SMP || BX_DEBUGGER
|
|
// The CHECK_MAX_INSTRUCTIONS macro allows cpu_loop to execute a few
|
|
// instructions and then return so that the other processors have a chance
|
|
// to run. This is used only when simulating multiple processors. If only
|
|
// one processor, don't waste any cycles on it! Also, it is not needed
|
|
// with the debugger because its guard mechanism provides the same
|
|
// functionality.
|
|
CHECK_MAX_INSTRUCTIONS(max_instr_count);
|
|
#endif
|
|
|
|
} // while (1)
|
|
}
|
|
|
|
unsigned BX_CPU_C::handleAsyncEvent(void)
|
|
{
|
|
//
|
|
// This area is where we process special conditions and events.
|
|
//
|
|
if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_HALT_STATE) {
|
|
// I made up the bitmask above to mean HALT state.
|
|
#if BX_SUPPORT_SMP == 0
|
|
// for one processor, pass the time as quickly as possible until
|
|
// an interrupt wakes up the CPU.
|
|
#if BX_DEBUGGER
|
|
while (bx_guard.interrupt_requested != 1)
|
|
#else
|
|
while (1)
|
|
#endif
|
|
{
|
|
if ((BX_CPU_INTR && BX_CPU_THIS_PTR get_IF()) ||
|
|
BX_CPU_THIS_PTR nmi_pending || BX_CPU_THIS_PTR smi_pending)
|
|
{
|
|
// interrupt ends the HALT condition
|
|
BX_CPU_THIS_PTR debug_trap = 0; // clear traps for after resume
|
|
BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
|
|
break;
|
|
}
|
|
if ((BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_HALT_STATE) == 0) {
|
|
BX_INFO(("handleAsyncEvent: reset detected in HLT state"));
|
|
break;
|
|
}
|
|
BX_TICK1();
|
|
}
|
|
#else /* BX_SUPPORT_SMP */
|
|
// for multiprocessor simulation, even if this CPU is halted we still
|
|
// must give the others a chance to simulate. If an interrupt has
|
|
// arrived, then clear the HALT condition; otherwise just return from
|
|
// the CPU loop with stop_reason STOP_CPU_HALTED.
|
|
if ((BX_CPU_INTR && BX_CPU_THIS_PTR get_IF()) ||
|
|
BX_CPU_THIS_PTR nmi_pending || BX_CPU_THIS_PTR smi_pending)
|
|
{
|
|
// interrupt ends the HALT condition
|
|
BX_CPU_THIS_PTR debug_trap = 0; // clear traps for after resume
|
|
BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
|
|
} else {
|
|
// HALT condition remains, return so other CPUs have a chance
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR stop_reason = STOP_CPU_HALTED;
|
|
#endif
|
|
return 1; // Return to caller of cpu_loop.
|
|
}
|
|
#endif
|
|
} else if (bx_pc_system.kill_bochs_request) {
|
|
// setting kill_bochs_request causes the cpu loop to return ASAP.
|
|
return 1; // Return to caller of cpu_loop.
|
|
}
|
|
|
|
// Priority 1: Hardware Reset and Machine Checks
|
|
// RESET
|
|
// Machine Check
|
|
// (bochs doesn't support these)
|
|
|
|
// Priority 2: Trap on Task Switch
|
|
// T flag in TSS is set
|
|
if (BX_CPU_THIS_PTR debug_trap & 0x00008000) {
|
|
BX_CPU_THIS_PTR dr6 |= BX_CPU_THIS_PTR debug_trap;
|
|
exception(BX_DB_EXCEPTION, 0, 0); // no error, not interrupt
|
|
}
|
|
|
|
// Priority 3: External Hardware Interventions
|
|
// FLUSH
|
|
// STOPCLK
|
|
// SMI
|
|
// INIT
|
|
// (bochs doesn't support these)
|
|
if (BX_CPU_THIS_PTR smi_pending && ! BX_CPU_THIS_PTR smm_mode())
|
|
{
|
|
// clear SMI pending flag and disable NMI when SMM was accepted
|
|
BX_CPU_THIS_PTR smi_pending = 0;
|
|
BX_CPU_THIS_PTR nmi_disable = 1;
|
|
enter_system_management_mode();
|
|
}
|
|
|
|
// Priority 4: Traps on Previous Instruction
|
|
// Breakpoints
|
|
// Debug Trap Exceptions (TF flag set or data/IO breakpoint)
|
|
if (BX_CPU_THIS_PTR debug_trap &&
|
|
!(BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG))
|
|
{
|
|
// A trap may be inhibited on this boundary due to an instruction
|
|
// which loaded SS. If so we clear the inhibit_mask below
|
|
// and don't execute this code until the next boundary.
|
|
// Commit debug events to DR6
|
|
BX_CPU_THIS_PTR dr6 |= BX_CPU_THIS_PTR debug_trap;
|
|
exception(BX_DB_EXCEPTION, 0, 0); // no error, not interrupt
|
|
}
|
|
|
|
// Priority 5: External Interrupts
|
|
// NMI Interrupts
|
|
// Maskable Hardware Interrupts
|
|
if (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_INTERRUPTS) {
|
|
// Processing external interrupts is inhibited on this
|
|
// boundary because of certain instructions like STI.
|
|
// inhibit_mask is cleared below, in which case we will have
|
|
// an opportunity to check interrupts on the next instruction
|
|
// boundary.
|
|
}
|
|
else if (BX_CPU_THIS_PTR nmi_pending) {
|
|
BX_CPU_THIS_PTR nmi_pending = 0;
|
|
BX_CPU_THIS_PTR nmi_disable = 1;
|
|
BX_CPU_THIS_PTR errorno = 0;
|
|
BX_CPU_THIS_PTR EXT = 1; /* external event */
|
|
interrupt(2, 0, 0, 0);
|
|
BX_INSTR_HWINTERRUPT(BX_CPU_ID, 2, BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
}
|
|
else if (BX_CPU_INTR && BX_CPU_THIS_PTR get_IF() && BX_DBG_ASYNC_INTR)
|
|
{
|
|
Bit8u vector;
|
|
|
|
// NOTE: similar code in ::take_irq()
|
|
#if BX_SUPPORT_APIC
|
|
if (BX_CPU_THIS_PTR local_apic.INTR)
|
|
vector = BX_CPU_THIS_PTR local_apic.acknowledge_int ();
|
|
else
|
|
vector = DEV_pic_iac(); // may set INTR with next interrupt
|
|
#else
|
|
// if no local APIC, always acknowledge the PIC.
|
|
vector = DEV_pic_iac(); // may set INTR with next interrupt
|
|
#endif
|
|
BX_CPU_THIS_PTR errorno = 0;
|
|
BX_CPU_THIS_PTR EXT = 1; /* external event */
|
|
interrupt(vector, 0, 0, 0);
|
|
BX_INSTR_HWINTERRUPT(BX_CPU_ID, vector,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
// Set up environment, as would be when this main cpu loop gets
|
|
// invoked. At the end of normal instructions, we always commmit
|
|
// the new EIP/ESP values. But here, we call interrupt() much like
|
|
// it was a sofware interrupt instruction, and need to effect the
|
|
// commit here. This code mirrors similar code above.
|
|
BX_CPU_THIS_PTR prev_eip = RIP; // commit new RIP
|
|
BX_CPU_THIS_PTR prev_esp = RSP; // commit new RSP
|
|
BX_CPU_THIS_PTR EXT = 0;
|
|
BX_CPU_THIS_PTR errorno = 0;
|
|
}
|
|
else if (BX_HRQ && BX_DBG_ASYNC_DMA) {
|
|
// NOTE: similar code in ::take_dma()
|
|
// assert Hold Acknowledge (HLDA) and go into a bus hold state
|
|
DEV_dma_raise_hlda();
|
|
}
|
|
|
|
// Priority 6: Faults from fetching next instruction
|
|
// Code breakpoint fault
|
|
// Code segment limit violation (priority 7 on 486/Pentium)
|
|
// Code page fault (priority 7 on 486/Pentium)
|
|
// (handled in main decode loop)
|
|
|
|
// Priority 7: Faults from decoding next instruction
|
|
// Instruction length > 15 bytes
|
|
// Illegal opcode
|
|
// Coprocessor not available
|
|
// (handled in main decode loop etc)
|
|
|
|
// Priority 8: Faults on executing an instruction
|
|
// Floating point execution
|
|
// Overflow
|
|
// Bound error
|
|
// Invalid TSS
|
|
// Segment not present
|
|
// Stack fault
|
|
// General protection
|
|
// Data page fault
|
|
// Alignment check
|
|
// (handled by rest of the code)
|
|
|
|
if (BX_CPU_THIS_PTR get_TF())
|
|
{
|
|
// TF is set before execution of next instruction. Schedule
|
|
// a debug trap (#DB) after execution. After completion of
|
|
// next instruction, the code above will invoke the trap.
|
|
BX_CPU_THIS_PTR debug_trap |= 0x00004000; // BS flag in DR6
|
|
}
|
|
|
|
// Now we can handle things which are synchronous to instruction
|
|
// execution.
|
|
if (BX_CPU_THIS_PTR get_RF()) {
|
|
BX_CPU_THIS_PTR clear_RF();
|
|
}
|
|
#if BX_X86_DEBUGGER
|
|
else {
|
|
// only bother comparing if any breakpoints enabled
|
|
if (BX_CPU_THIS_PTR dr7 & 0x000000ff) {
|
|
Bit32u iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_eip;
|
|
Bit32u dr6_bits;
|
|
if ( (dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction,
|
|
BX_HWDebugInstruction)) )
|
|
{
|
|
// Add to the list of debug events thus far.
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
BX_CPU_THIS_PTR debug_trap |= dr6_bits;
|
|
// If debug events are not inhibited on this boundary,
|
|
// fire off a debug fault. Otherwise handle it on the next
|
|
// boundary. (becomes a trap)
|
|
if ( !(BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG) ) {
|
|
// Commit debug events to DR6
|
|
BX_CPU_THIS_PTR dr6 = BX_CPU_THIS_PTR debug_trap;
|
|
exception(BX_DB_EXCEPTION, 0, 0); // no error, not interrupt
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// We have ignored processing of external interrupts and
|
|
// debug events on this boundary. Reset the mask so they
|
|
// will be processed on the next boundary.
|
|
BX_CPU_THIS_PTR inhibit_mask = 0;
|
|
|
|
if ( !(BX_CPU_INTR ||
|
|
BX_CPU_THIS_PTR debug_trap ||
|
|
BX_HRQ ||
|
|
BX_CPU_THIS_PTR get_TF()
|
|
#if BX_X86_DEBUGGER
|
|
|| (BX_CPU_THIS_PTR dr7 & 0xff)
|
|
#endif
|
|
))
|
|
BX_CPU_THIS_PTR async_event = 0;
|
|
|
|
return 0; // Continue executing cpu_loop.
|
|
}
|
|
|
|
|
|
// boundaries of consideration:
|
|
//
|
|
// * physical memory boundary: 1024k (1Megabyte) (increments of...)
|
|
// * A20 boundary: 1024k (1Megabyte)
|
|
// * page boundary: 4k
|
|
// * ROM boundary: 2k (dont care since we are only reading)
|
|
// * segment boundary: any
|
|
|
|
void BX_CPU_C::prefetch(void)
|
|
{
|
|
bx_address temp_rip = RIP;
|
|
bx_address laddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + temp_rip;
|
|
bx_phy_address pAddr;
|
|
|
|
// Calculate RIP at the beginning of the page.
|
|
bx_address eipPageOffset0 = RIP - (laddr & 0xfff);
|
|
BX_CPU_THIS_PTR eipPageBias = -eipPageOffset0;
|
|
BX_CPU_THIS_PTR eipPageWindowSize = 4096;
|
|
|
|
if (! Is64BitMode()) {
|
|
Bit32u temp_limit = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled;
|
|
if (((Bit32u) temp_rip) > temp_limit) {
|
|
BX_ERROR(("prefetch: EIP [%08x] > CS.limit [%08x]", (Bit32u) temp_rip, temp_limit));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
if (temp_limit + BX_CPU_THIS_PTR eipPageBias < 4096) {
|
|
BX_CPU_THIS_PTR eipPageWindowSize = temp_limit + BX_CPU_THIS_PTR eipPageBias + 1;
|
|
}
|
|
}
|
|
|
|
#if BX_SUPPORT_PAGING
|
|
if (BX_CPU_THIS_PTR cr0.pg) {
|
|
// aligned block guaranteed to be all in one page, same A20 address
|
|
pAddr = itranslate_linear(laddr, CPL==3);
|
|
pAddr = A20ADDR(pAddr);
|
|
}
|
|
else
|
|
#endif // BX_SUPPORT_PAGING
|
|
{
|
|
pAddr = A20ADDR(laddr);
|
|
}
|
|
|
|
BX_CPU_THIS_PTR pAddrA20Page = pAddr & 0xfffff000;
|
|
BX_CPU_THIS_PTR eipFetchPtr =
|
|
BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS,
|
|
BX_CPU_THIS_PTR pAddrA20Page, BX_READ, CODE_ACCESS);
|
|
|
|
// Sanity checks
|
|
if (! BX_CPU_THIS_PTR eipFetchPtr) {
|
|
if (pAddr >= BX_CPU_THIS_PTR mem->len) {
|
|
BX_PANIC(("prefetch: running in bogus memory, pAddr=0x%08x", pAddr));
|
|
}
|
|
else {
|
|
BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%08x", pAddr));
|
|
}
|
|
}
|
|
|
|
#if BX_SUPPORT_ICACHE
|
|
BX_CPU_THIS_PTR currPageWriteStampPtr = pageWriteStampTable.getPageWriteStampPtr(pAddr);
|
|
Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
|
|
Bit32u fetchModeMask = BX_CPU_THIS_PTR fetchModeMask;
|
|
if ((pageWriteStamp & ICacheFetchModeMask) != fetchModeMask)
|
|
{
|
|
// The current CPU mode does not match iCache entries for this
|
|
// physical page.
|
|
pageWriteStamp &= ICacheWriteStampMask; // Clear out old fetch mode bits.
|
|
pageWriteStamp |= fetchModeMask; // Add in new ones.
|
|
pageWriteStampTable.setPageWriteStamp(pAddr, pageWriteStamp);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::boundaryFetch(Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *i)
|
|
{
|
|
unsigned j;
|
|
Bit8u fetchBuffer[16]; // Really only need 15
|
|
unsigned ret;
|
|
|
|
if (remainingInPage >= 15) {
|
|
BX_INFO(("fetchDecode #GP(0): too many instruction prefixes"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
// Read all leftover bytes in current page up to boundary.
|
|
for (j=0; j<remainingInPage; j++) {
|
|
fetchBuffer[j] = *fetchPtr++;
|
|
}
|
|
|
|
// The 2nd chunk of the instruction is on the next page.
|
|
// Set RIP to the 0th byte of the 2nd page, and force a
|
|
// prefetch so direct access of that physical page is possible, and
|
|
// all the associated info is updated.
|
|
RIP += remainingInPage;
|
|
prefetch();
|
|
if (BX_CPU_THIS_PTR eipPageWindowSize < 15) {
|
|
BX_PANIC(("fetch_decode: small window size after prefetch"));
|
|
}
|
|
|
|
// We can fetch straight from the 0th byte, which is eipFetchPtr;
|
|
fetchPtr = BX_CPU_THIS_PTR eipFetchPtr;
|
|
|
|
// read leftover bytes in next page
|
|
for (; j<15; j++) {
|
|
fetchBuffer[j] = *fetchPtr++;
|
|
}
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
|
ret = fetchDecode64(fetchBuffer, i, 15);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
ret = fetchDecode(fetchBuffer, i, 15);
|
|
}
|
|
|
|
if (ret==0) {
|
|
BX_INFO(("fetchDecode #GP(0): too many instruction prefixes"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
// Restore EIP since we fudged it to start at the 2nd page boundary.
|
|
RIP = BX_CPU_THIS_PTR prev_eip;
|
|
|
|
// Since we cross an instruction boundary, note that we need a prefetch()
|
|
// again on the next instruction. Perhaps we can optimize this to
|
|
// eliminate the extra prefetch() since we do it above, but have to
|
|
// think about repeated instructions, etc.
|
|
invalidate_prefetch_q();
|
|
|
|
BX_INSTR_OPCODE(BX_CPU_ID, fetchBuffer, i->ilen(),
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, Is64BitMode());
|
|
}
|
|
|
|
void BX_CPU_C::deliver_NMI(void)
|
|
{
|
|
BX_CPU_THIS_PTR nmi_pending = 1;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
|
|
void BX_CPU_C::deliver_SMI(void)
|
|
{
|
|
BX_CPU_THIS_PTR smi_pending = 1;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
|
|
#if BX_EXTERNAL_DEBUGGER
|
|
|
|
void BX_CPU_C::ask(int level, const char *prefix, const char *fmt, va_list ap)
|
|
{
|
|
char buf1[1024];
|
|
vsprintf (buf1, fmt, ap);
|
|
printf ("%s %s\n", prefix, buf1);
|
|
trap_debugger(1);
|
|
}
|
|
|
|
void BX_CPU_C::trap_debugger(bx_bool callnow)
|
|
{
|
|
regs.debug_state = debug_step;
|
|
if (callnow) {
|
|
bx_external_debugger(BX_CPU_THIS);
|
|
}
|
|
}
|
|
|
|
#endif // #if BX_EXTERNAL_DEBUGGER
|
|
|
|
#if BX_DEBUGGER
|
|
extern unsigned dbg_show_mask;
|
|
|
|
bx_bool BX_CPU_C::dbg_is_begin_instr_bpoint(Bit16u cs, bx_address eip, bx_address laddr, bx_bool is_32, bx_bool is_64)
|
|
{
|
|
Bit64u tt = bx_pc_system.time_ticks();
|
|
|
|
BX_CPU_THIS_PTR guard_found.cs = cs;
|
|
BX_CPU_THIS_PTR guard_found.eip = eip;
|
|
BX_CPU_THIS_PTR guard_found.laddr = laddr;
|
|
BX_CPU_THIS_PTR guard_found.is_32bit_code = is_32;
|
|
BX_CPU_THIS_PTR guard_found.is_64bit_code = is_64;
|
|
|
|
// mode switch breakpoint
|
|
// instruction which generate exceptions never reach the end of the
|
|
// loop due to a long jump. Thats why we check at start of instr.
|
|
// Downside is that we show the instruction about to be executed
|
|
// (not the one generating the mode switch).
|
|
if (BX_CPU_THIS_PTR mode_break &&
|
|
(BX_CPU_THIS_PTR dbg_cpu_mode != BX_CPU_THIS_PTR get_cpu_mode()))
|
|
{
|
|
BX_INFO(("[" FMT_LL "d] Caught mode switch breakpoint, switching from '%s' to '%s'",
|
|
bx_pc_system.time_ticks(), cpu_mode_string(BX_CPU_THIS_PTR dbg_cpu_mode),
|
|
cpu_mode_string(BX_CPU_THIS_PTR get_cpu_mode())));
|
|
BX_CPU_THIS_PTR dbg_cpu_mode = BX_CPU_THIS_PTR get_cpu_mode();
|
|
BX_CPU_THIS_PTR stop_reason = STOP_MODE_BREAK_POINT;
|
|
return(1);
|
|
}
|
|
|
|
// support for 'show' command in debugger
|
|
if(dbg_show_mask) {
|
|
int rv = bx_dbg_show_symbolic();
|
|
if (rv) return(rv);
|
|
}
|
|
|
|
// see if debugger is looking for iaddr breakpoint of any type
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_ALL) {
|
|
#if BX_DBG_SUPPORT_VIR_BPOINT
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_VIR) {
|
|
if ((BX_CPU_THIS_PTR guard_found.icount!=0) ||
|
|
(tt != BX_CPU_THIS_PTR guard_found.time_tick))
|
|
{
|
|
for (unsigned i=0; i<bx_guard.iaddr.num_virtual; i++) {
|
|
if (bx_guard.iaddr.vir[i].enabled &&
|
|
(bx_guard.iaddr.vir[i].cs == cs) &&
|
|
(bx_guard.iaddr.vir[i].eip == eip))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_IADDR_VIR;
|
|
BX_CPU_THIS_PTR guard_found.iaddr_index = i;
|
|
BX_CPU_THIS_PTR guard_found.time_tick = tt;
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|
return(1); // on a breakpoint
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_DBG_SUPPORT_LIN_BPOINT
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_LIN) {
|
|
if ((BX_CPU_THIS_PTR guard_found.icount!=0) ||
|
|
(tt != BX_CPU_THIS_PTR guard_found.time_tick))
|
|
{
|
|
for (unsigned i=0; i<bx_guard.iaddr.num_linear; i++) {
|
|
if (bx_guard.iaddr.lin[i].enabled &&
|
|
(bx_guard.iaddr.lin[i].addr == BX_CPU_THIS_PTR guard_found.laddr))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_IADDR_LIN;
|
|
BX_CPU_THIS_PTR guard_found.iaddr_index = i;
|
|
BX_CPU_THIS_PTR guard_found.time_tick = tt;
|
|
return(1); // on a breakpoint
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
#if BX_DBG_SUPPORT_PHY_BPOINT
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_PHY) {
|
|
Bit32u phy;
|
|
bx_bool valid;
|
|
dbg_xlate_linear2phy(BX_CPU_THIS_PTR guard_found.laddr, &phy, &valid);
|
|
// The "guard_found.icount!=0" condition allows you to step or
|
|
// continue beyond a breakpoint. Bryce tried removing it once,
|
|
// and once you get to a breakpoint you are stuck there forever.
|
|
// Not pretty.
|
|
if (valid && ((BX_CPU_THIS_PTR guard_found.icount!=0) ||
|
|
(tt != BX_CPU_THIS_PTR guard_found.time_tick)))
|
|
{
|
|
for (unsigned i=0; i<bx_guard.iaddr.num_physical; i++) {
|
|
if (bx_guard.iaddr.phy[i].enabled && (bx_guard.iaddr.phy[i].addr == phy))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_IADDR_PHY;
|
|
BX_CPU_THIS_PTR guard_found.iaddr_index = i;
|
|
BX_CPU_THIS_PTR guard_found.time_tick = tt;
|
|
return(1); // on a breakpoint
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return(0); // not on a breakpoint
|
|
}
|
|
|
|
bx_bool BX_CPU_C::dbg_is_end_instr_bpoint(Bit16u cs, bx_address eip, bx_address laddr, bx_bool is_32, bx_bool is_64)
|
|
{
|
|
//fprintf (stderr, "end_instr_bp: checking for icount or ^C\n");
|
|
BX_CPU_THIS_PTR guard_found.icount++;
|
|
BX_CPU_THIS_PTR guard_found.cs = cs;
|
|
BX_CPU_THIS_PTR guard_found.eip = eip;
|
|
BX_CPU_THIS_PTR guard_found.laddr = laddr;
|
|
BX_CPU_THIS_PTR guard_found.is_32bit_code = is_32;
|
|
|
|
// convenient point to see if user typed Ctrl-C
|
|
if (bx_guard.interrupt_requested &&
|
|
(bx_guard.guard_for & BX_DBG_GUARD_CTRL_C))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_CTRL_C;
|
|
return(1);
|
|
}
|
|
|
|
return(0); // no breakpoint
|
|
}
|
|
|
|
void BX_CPU_C::dbg_take_irq(void)
|
|
{
|
|
// NOTE: similar code in ::cpu_loop()
|
|
|
|
if ( BX_CPU_INTR && BX_CPU_THIS_PTR get_IF() ) {
|
|
if ( setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0 ) {
|
|
// normal return from setjmp setup
|
|
unsigned vector = DEV_pic_iac(); // may set INTR with next interrupt
|
|
BX_CPU_THIS_PTR errorno = 0;
|
|
BX_CPU_THIS_PTR EXT = 1; // external event
|
|
BX_CPU_THIS_PTR async_event = 1; // set in case INTR is triggered
|
|
interrupt(vector, 0, 0, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::dbg_force_interrupt(unsigned vector)
|
|
{
|
|
// Used to force slave simulator to take an interrupt, without
|
|
// regard to IF
|
|
|
|
if ( setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0 ) {
|
|
// normal return from setjmp setup
|
|
BX_CPU_THIS_PTR errorno = 0;
|
|
BX_CPU_THIS_PTR EXT = 1; // external event
|
|
BX_CPU_THIS_PTR async_event = 1; // probably don't need this
|
|
interrupt(vector, 0, 0, 0);
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::dbg_take_dma(void)
|
|
{
|
|
// NOTE: similar code in ::cpu_loop()
|
|
if (BX_HRQ) {
|
|
BX_CPU_THIS_PTR async_event = 1; // set in case INTR is triggered
|
|
DEV_dma_raise_hlda();
|
|
}
|
|
}
|
|
|
|
#endif // #if BX_DEBUGGER
|