309 lines
12 KiB
C
Executable File
309 lines
12 KiB
C
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id: smm.h,v 1.5 2008-02-02 21:46:53 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2006 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_SMM_H
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#define BX_SMM_H
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/* SMM feature masks */
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#define SMM_IO_INSTRUCTION_RESTART (0x00010000)
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#define SMM_SMBASE_RELOCATION (0x00020000)
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#define SMM_SAVE_STATE_MAP_SIZE 128
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#if BX_SUPPORT_X86_64
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// for x86-64 configuration using AMD Athlon 64 512-byte SMM save state map
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// revision ID according to QEMU/Bochs BIOS
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#define SMM_REVISION_ID (0x00000064 | SMM_SMBASE_RELOCATION)
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#define SMRAM_OFFSET_RAX_HI32 0x7ffc
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#define SMRAM_OFFSET_RAX_LO32 0x7ff8
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#define SMRAM_OFFSET_RCX_HI32 0x7ff4
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#define SMRAM_OFFSET_RCX_LO32 0x7ff0
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#define SMRAM_OFFSET_RDX_HI32 0x7fec
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#define SMRAM_OFFSET_RDX_LO32 0x7fe8
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#define SMRAM_OFFSET_RBX_HI32 0x7fe4
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#define SMRAM_OFFSET_RBX_LO32 0x7fe0
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#define SMRAM_OFFSET_RSP_HI32 0x7fdc
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#define SMRAM_OFFSET_RSP_LO32 0x7fd8
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#define SMRAM_OFFSET_RBP_HI32 0x7fd4
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#define SMRAM_OFFSET_RBP_LO32 0x7fd0
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#define SMRAM_OFFSET_RSI_HI32 0x7fcc
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#define SMRAM_OFFSET_RSI_LO32 0x7fc8
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#define SMRAM_OFFSET_RDI_HI32 0x7fc4
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#define SMRAM_OFFSET_RDI_LO32 0x7fc0
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#define SMRAM_OFFSET_R8_HI32 0x7fbc
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#define SMRAM_OFFSET_R8_LO32 0x7fb8
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#define SMRAM_OFFSET_R9_HI32 0x7fb4
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#define SMRAM_OFFSET_R9_LO32 0x7fb0
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#define SMRAM_OFFSET_R10_HI32 0x7fac
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#define SMRAM_OFFSET_R10_LO32 0x7fa8
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#define SMRAM_OFFSET_R11_HI32 0x7fa4
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#define SMRAM_OFFSET_R11_LO32 0x7fa0
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#define SMRAM_OFFSET_R12_HI32 0x7f9c
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#define SMRAM_OFFSET_R12_LO32 0x7f98
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#define SMRAM_OFFSET_R13_HI32 0x7f94
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#define SMRAM_OFFSET_R13_LO32 0x7f90
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#define SMRAM_OFFSET_R14_HI32 0x7f8c
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#define SMRAM_OFFSET_R14_LO32 0x7f88
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#define SMRAM_OFFSET_R15_HI32 0x7f84
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#define SMRAM_OFFSET_R15_LO32 0x7f80
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#define SMRAM_OFFSET_RIP_HI32 0x7f7c
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#define SMRAM_OFFSET_RIP_LO32 0x7f78
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// Hi32 part of RFLAGS64 0x7f74 (always zero)
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#define SMRAM_OFFSET_RFLAGS32 0x7f70
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// Hi32 part of 64-bit DR6 0x7f6c (always zero)
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#define SMRAM_OFFSET_DR6 0x7f68
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// Hi32 part of 64-bit DR7 0x7f64 (always zero)
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#define SMRAM_OFFSET_DR7 0x7f60
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// Hi32 part of 64-bit CR0 0x7f5c (always zero)
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#define SMRAM_OFFSET_CR0 0x7f58
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// Hi32 part of 64-bit CR3 0x7f54 (always zero, 32-bit physical address)
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#define SMRAM_OFFSET_CR3 0x7f50
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// Hi32 part of 64-bit CR4 0x7f4c (always zero)
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#define SMRAM_OFFSET_CR4 0x7f48
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// reserved 0x7f44
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// reserved 0x7f40
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// reserved 0x7f3c
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// reserved 0x7f38
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// reserved 0x7f34
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// reserved 0x7f30
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// reserved 0x7f2c
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// reserved 0x7f28
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// reserved 0x7f24
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// reserved 0x7f20
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// reserved 0x7f1c
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// reserved 0x7f18
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// reserved 0x7f14
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// reserved 0x7f10
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// reserved 0x7f0c
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// reserved 0x7f08
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// reserved 0x7f04
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#define SMRAM_SMBASE_OFFSET 0x7f00
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#define SMRAM_SMM_REVISION_ID 0x7efc
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// reserved 0x7ef8
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// reserved 0x7ef4
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// reserved 0x7ef0
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// reserved 0x7eec
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// reserved 0x7ee8
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// reserved 0x7ee4
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// reserved 0x7ee0
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// reserved 0x7edc
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// reserved 0x7ed8
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// High part of 64-bit EFER 0x7ed4 (always zero)
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#define SMRAM_OFFSET_EFER 0x7ed0
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// reserved 0x7ecc
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#define SMRAM_IO_INSTRUCTION_RESTART 0x7ec8
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#define SMRAM_AUTOHALT_RESTART 0x7ec8
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#define SMRAM_NMI_MASK 0x7ec8
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// reserved 0x7ec4
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#define SMRAM_SMM_IO_TRAP 0x7ec0
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// reserved 0x7ebc
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// reserved 0x7eb8
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// reserved 0x7eb4
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// reserved 0x7eb0
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// reserved 0x7eac
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// reserved 0x7ea8
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// reserved 0x7ea4
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// reserved 0x7ea0
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#define SMRAM_TR_BASE_HI32 0x7e9c
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#define SMRAM_TR_BASE_LO32 0x7e98
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#define SMRAM_TR_LIMIT 0x7e94
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#define SMRAM_TR_SELECTOR_AR 0x7e90
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#define SMRAM_IDTR_BASE_HI32 0x7e8c
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#define SMRAM_IDTR_BASE_LO32 0x7e88
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#define SMRAM_IDTR_LIMIT 0x7e84
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// reserved 0x7e80
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#define SMRAM_LDTR_BASE_HI32 0x7e7c
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#define SMRAM_LDTR_BASE_LO32 0x7e78
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#define SMRAM_LDTR_LIMIT 0x7e74
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#define SMRAM_LDTR_SELECTOR_AR 0x7e70
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#define SMRAM_GDTR_BASE_HI32 0x7e6c
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#define SMRAM_GDTR_BASE_LO32 0x7e68
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#define SMRAM_GDTR_LIMIT 0x7e64
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// reserved 0x7e60
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#define SMRAM_GS_BASE_HI32 0x7e5c
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#define SMRAM_GS_BASE_LO32 0x7e58
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#define SMRAM_GS_LIMIT 0x7e54
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#define SMRAM_GS_SELECTOR_AR 0x7e50
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#define SMRAM_FS_BASE_HI32 0x7e4c
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#define SMRAM_FS_BASE_LO32 0x7e48
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#define SMRAM_FS_LIMIT 0x7e44
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#define SMRAM_FS_SELECTOR_AR 0x7e40
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#define SMRAM_DS_BASE_HI32 0x7e3c
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#define SMRAM_DS_BASE_LO32 0x7e38
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#define SMRAM_DS_LIMIT 0x7e34
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#define SMRAM_DS_SELECTOR_AR 0x7e30
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#define SMRAM_SS_BASE_HI32 0x7e2c
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#define SMRAM_SS_BASE_LO32 0x7e28
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#define SMRAM_SS_LIMIT 0x7e24
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#define SMRAM_SS_SELECTOR_AR 0x7e20
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#define SMRAM_CS_BASE_HI32 0x7e1c
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#define SMRAM_CS_BASE_LO32 0x7e18
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#define SMRAM_CS_LIMIT 0x7e14
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#define SMRAM_CS_SELECTOR_AR 0x7e10
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#define SMRAM_ES_BASE_HI32 0x7e0c
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#define SMRAM_ES_BASE_LO32 0x7e08
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#define SMRAM_ES_LIMIT 0x7e04
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#define SMRAM_ES_SELECTOR_AR 0x7e00
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#else /* BX_SUPPORT_X86_64 == 0 */
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// for x86-32 configuration using Intel P6 512-byte SMM save state map
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#define SMM_REVISION_ID (0x00000000 | SMM_SMBASE_RELOCATION)
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// source for Intel P6 SMM save state map used: www.sandpile.org
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#define SMRAM_OFFSET_CR0 0x7ffc
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#define SMRAM_OFFSET_CR3 0x7ff8
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#define SMRAM_OFFSET_EFLAGS 0x7ff4
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#define SMRAM_OFFSET_EIP 0x7ff0
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#define SMRAM_OFFSET_EDI 0x7fec
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#define SMRAM_OFFSET_ESI 0x7fe8
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#define SMRAM_OFFSET_EBP 0x7fe4
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#define SMRAM_OFFSET_ESP 0x7fe0
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#define SMRAM_OFFSET_EBX 0x7fdc
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#define SMRAM_OFFSET_EDX 0x7fd8
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#define SMRAM_OFFSET_ECX 0x7fd4
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#define SMRAM_OFFSET_EAX 0x7fd0
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#define SMRAM_OFFSET_DR6 0x7fcc
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#define SMRAM_OFFSET_DR7 0x7fc8
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#define SMRAM_TR_SELECTOR 0x7fc4
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#define SMRAM_LDTR_SELECTOR 0x7fc0
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#define SMRAM_GS_SELECTOR 0x7fbc
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#define SMRAM_FS_SELECTOR 0x7fb8
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#define SMRAM_DS_SELECTOR 0x7fb4
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#define SMRAM_SS_SELECTOR 0x7fb0
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#define SMRAM_CS_SELECTOR 0x7fac
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#define SMRAM_ES_SELECTOR 0x7fa8
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#define SMRAM_SS_BASE 0x7fa4
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#define SMRAM_SS_LIMIT 0x7fa0
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#define SMRAM_SS_SELECTOR_AR 0x7f9c
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#define SMRAM_CS_BASE 0x7f98
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#define SMRAM_CS_LIMIT 0x7f94
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#define SMRAM_CS_SELECTOR_AR 0x7f90
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#define SMRAM_ES_BASE 0x7f8c
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#define SMRAM_ES_LIMIT 0x7f88
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#define SMRAM_ES_SELECTOR_AR 0x7f84
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#define SMRAM_LDTR_BASE 0x7f80
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#define SMRAM_LDTR_LIMIT 0x7f7c
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#define SMRAM_LDTR_SELECTOR_AR 0x7f78
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#define SMRAM_GDTR_BASE 0x7f74
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#define SMRAM_GDTR_LIMIT 0x7f70
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// reserved 0x7f6c
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// reserved 0x7f68
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#define SMRAM_TR_BASE 0x7f64
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#define SMRAM_TR_LIMIT 0x7f60
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#define SMRAM_TR_SELECTOR_AR 0x7f5c
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#define SMRAM_IDTR_BASE 0x7f58
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#define SMRAM_IDTR_LIMIT 0x7f54
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// reserved 0x7f50
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#define SMRAM_GS_BASE 0x7f4c
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#define SMRAM_GS_LIMIT 0x7f48
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#define SMRAM_GS_SELECTOR_AR 0x7f44
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#define SMRAM_FS_BASE 0x7f40
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#define SMRAM_FS_LIMIT 0x7f3c
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#define SMRAM_FS_SELECTOR_AR 0x7f38
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#define SMRAM_DS_BASE 0x7f34
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#define SMRAM_DS_LIMIT 0x7f30
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#define SMRAM_DS_SELECTOR_AR 0x7f2c
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// reserved 0x7f28
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// reserved 0x7f24
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// reserved 0x7f20
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// reserved 0x7f1c
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// reserved 0x7f18
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#define SMRAM_OFFSET_CR4 0x7f14
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// reserved 0x7f10 (used for I/O restart)
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// reserved 0x7f0c (used for I/O restart)
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// reserved 0x7f08 (used for I/O restart)
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// reserved 0x7f04 (used for I/O restart)
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#define SMRAM_IO_INSTRUCTION_RESTART 0x7f00
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#define SMRAM_AUTOHALT_RESTART 0x7f00
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#define SMRAM_SMM_REVISION_ID 0x7efc
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#define SMRAM_SMBASE_OFFSET 0x7ef8
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// reserved 0x7ef4
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// reserved 0x7ef0
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// reserved 0x7eec
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// reserved 0x7ee8
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// reserved 0x7ee4
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// reserved 0x7ee0
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// reserved 0x7edc
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// reserved 0x7ed8
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// reserved 0x7ed4
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// reserved 0x7ed0
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// reserved 0x7ecc
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// reserved 0x7ec8
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// reserved 0x7ec4
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// reserved 0x7ec0
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// reserved 0x7ebc
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// reserved 0x7eb8
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// reserved 0x7eb4
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// reserved 0x7eb0
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// reserved 0x7eac
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// reserved 0x7ea8
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// reserved 0x7ea4
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// reserved 0x7ea0
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// reserved 0x7e9c
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// reserved 0x7e98
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// reserved 0x7e94
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// reserved 0x7e90
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// reserved 0x7e8c
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// reserved 0x7e88
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// reserved 0x7e84
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// reserved 0x7e80
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// reserved 0x7e7c
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// reserved 0x7e78
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// reserved 0x7e74
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// reserved 0x7e70
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// reserved 0x7e6c
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// reserved 0x7e68
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// reserved 0x7e64
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// reserved 0x7e60
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// reserved 0x7e5c
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// reserved 0x7e58
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// reserved 0x7e54
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// reserved 0x7e50
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// reserved 0x7e4c
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// reserved 0x7e48
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// reserved 0x7e44
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// reserved 0x7e40
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// reserved 0x7e3c
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// reserved 0x7e38
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// reserved 0x7e34
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// reserved 0x7e30
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// reserved 0x7e2c
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// reserved 0x7e28
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// reserved 0x7e24
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// reserved 0x7e20
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// reserved 0x7e1c
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// reserved 0x7e18
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// reserved 0x7e14
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// reserved 0x7e10
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// reserved 0x7e0c
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// reserved 0x7e08
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// reserved 0x7e04
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// reserved 0x7e00
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#endif /* BX_SUPPORT_X86_64 */
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#endif
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