384 lines
11 KiB
C++
384 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: memory.cc,v 1.62 2007-11-01 18:03:48 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#include "cpu/cpu.h"
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#include "iodev/iodev.h"
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#define LOG_THIS BX_MEM_THIS
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#if BX_PROVIDE_CPU_MEMORY
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//
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// Memory map inside the 1st megabyte:
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//
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// 0x00000 - 0x7ffff DOS area (512K)
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// 0x80000 - 0x9ffff Optional fixed memory hole (128K)
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// 0xa0000 - 0xbffff Standard PCI/ISA Video Mem / SMMRAM (128K)
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// 0xc0000 - 0xdffff Expansion Card BIOS and Buffer Area (128K)
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// 0xe0000 - 0xeffff Lower BIOS Area (64K)
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// 0xf0000 - 0xfffff Upper BIOS Area (64K)
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//
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void BX_CPP_AttrRegparmN(3)
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BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len, void *data)
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{
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Bit8u *data_ptr;
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bx_phy_address a20addr = A20ADDR(addr);
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struct memory_handler_struct *memory_handler = NULL;
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// Note: accesses should always be contained within a single page now
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if (cpu != NULL) {
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#if BX_SUPPORT_IODEBUG
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bx_iodebug_c::mem_write(cpu, a20addr, len, data);
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#endif
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BX_INSTR_PHY_WRITE(cpu->which_cpu(), a20addr, len);
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#if BX_DEBUGGER
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// (mch) Check for physical write break points, TODO
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// (bbd) Each breakpoint should have an associated CPU#, TODO
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for (unsigned i = 0; i < num_write_watchpoints; i++) {
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if (write_watchpoint[i] == a20addr) {
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cpu->watchpoint = a20addr;
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cpu->break_point = BREAK_POINT_WRITE;
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break;
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}
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}
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#endif
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#if BX_SUPPORT_APIC
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bx_generic_apic_c *local_apic = &cpu->local_apic;
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if (local_apic->is_selected(a20addr, len)) {
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local_apic->write(a20addr, (Bit32u *)data, len);
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return;
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}
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#endif
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if ((a20addr & 0xfffe0000) == 0x000a0000 && (BX_MEM_THIS smram_available))
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{
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// SMRAM memory space
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if (BX_MEM_THIS smram_enable || (cpu->smm_mode() && !BX_MEM_THIS smram_restricted))
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goto mem_write;
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}
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}
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#if BX_SUPPORT_MONITOR_MWAIT
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BX_MEM_THIS check_monitor(a20addr, len);
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#endif
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memory_handler = BX_MEM_THIS memory_handlers[a20addr >> 20];
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while (memory_handler) {
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if (memory_handler->begin <= a20addr &&
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memory_handler->end >= a20addr &&
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memory_handler->write_handler(a20addr, len, data, memory_handler->param))
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{
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return;
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}
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memory_handler = memory_handler->next;
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}
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mem_write:
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// all memory access feets in single 4K page
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if (a20addr < BX_MEM_THIS len) {
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#if BX_SUPPORT_ICACHE
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pageWriteStampTable.decWriteStamp(a20addr);
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#endif
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// all of data is within limits of physical memory
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if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
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{
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if (len == 8) {
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WriteHostQWordToLittleEndian(&BX_MEM_THIS vector[a20addr], *(Bit64u*)data);
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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if (len == 4) {
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WriteHostDWordToLittleEndian(&BX_MEM_THIS vector[a20addr], *(Bit32u*)data);
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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if (len == 2) {
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WriteHostWordToLittleEndian(&BX_MEM_THIS vector[a20addr], *(Bit16u*)data);
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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if (len == 1) {
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* ((Bit8u *) (&BX_MEM_THIS vector[a20addr])) = * (Bit8u *) data;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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// len == other, just fall thru to special cases handling
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}
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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write_one:
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if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
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{
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// addr *not* in range 000A0000 .. 000FFFFF
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BX_MEM_THIS vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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inc_one:
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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goto write_one;
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}
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// addr must be in range 000A0000 .. 000FFFFF
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// SMMRAM
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if (a20addr <= 0x000bffff) {
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// devices are not allowed to access SMMRAM under VGA memory
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if (cpu) {
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BX_MEM_THIS vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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}
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goto inc_one;
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}
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// adapter ROM C0000 .. DFFFF
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// ROM BIOS memory E0000 .. FFFFF
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#if BX_SUPPORT_PCI == 0
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// ignore write to ROM
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#else
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// Write Based on 440fx Programming
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if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
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{
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switch (DEV_pci_wr_memtype(a20addr)) {
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case 0x1: // Writes to ShadowRAM
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BX_DEBUG(("Writing to ShadowRAM: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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BX_MEM_THIS vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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goto inc_one;
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case 0x0: // Writes to ROM, Inhibit
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BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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default:
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BX_PANIC(("writePhysicalPage: default case"));
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goto inc_one;
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}
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}
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#endif
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goto inc_one;
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}
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else {
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// access outside limits of physical memory, ignore
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BX_DEBUG(("Write outside the limits of physical memory (0x%08x) (ignore)", a20addr));
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}
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}
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void BX_CPP_AttrRegparmN(3)
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BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len, void *data)
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{
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Bit8u *data_ptr;
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bx_phy_address a20addr = A20ADDR(addr);
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struct memory_handler_struct *memory_handler = NULL;
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// Note: accesses should always be contained within a single page now
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if (cpu != NULL) {
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#if BX_SUPPORT_IODEBUG
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bx_iodebug_c::mem_read(cpu, a20addr, len, data);
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#endif
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BX_INSTR_PHY_READ(cpu->which_cpu(), a20addr, len);
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#if BX_DEBUGGER
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// (mch) Check for physical read break points, TODO
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// (bbd) Each breakpoint should have an associated CPU#, TODO
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for (unsigned i = 0; i < num_read_watchpoints; i++) {
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if (read_watchpoint[i] == a20addr) {
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cpu->watchpoint = a20addr;
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cpu->break_point = BREAK_POINT_READ;
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break;
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}
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}
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#endif
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#if BX_SUPPORT_APIC
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bx_generic_apic_c *local_apic = &cpu->local_apic;
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if (local_apic->is_selected (a20addr, len)) {
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local_apic->read(a20addr, data, len);
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return;
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}
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#endif
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if ((a20addr & 0xfffe0000) == 0x000a0000 && (BX_MEM_THIS smram_available))
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{
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// SMRAM memory space
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if (BX_MEM_THIS smram_enable || (cpu->smm_mode() && !BX_MEM_THIS smram_restricted))
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goto mem_read;
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}
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}
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memory_handler = BX_MEM_THIS memory_handlers[a20addr >> 20];
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while (memory_handler) {
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if (memory_handler->begin <= a20addr &&
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memory_handler->end >= a20addr &&
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memory_handler->read_handler(a20addr, len, data, memory_handler->param))
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{
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return;
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}
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memory_handler = memory_handler->next;
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}
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mem_read:
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if (a20addr <= BX_MEM_THIS len) {
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// all of data is within limits of physical memory
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if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
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{
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if (len == 8) {
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ReadHostQWordFromLittleEndian(&BX_MEM_THIS vector[a20addr], * (Bit64u*) data);
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return;
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}
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if (len == 4) {
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ReadHostDWordFromLittleEndian(&BX_MEM_THIS vector[a20addr], * (Bit32u*) data);
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return;
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}
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if (len == 2) {
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ReadHostWordFromLittleEndian(&BX_MEM_THIS vector[a20addr], * (Bit16u*) data);
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return;
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}
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if (len == 1) {
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* (Bit8u *) data = * ((Bit8u *) (&BX_MEM_THIS vector[a20addr]));
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return;
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}
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// len == other case can just fall thru to special cases handling
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}
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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read_one:
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if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
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{
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// addr *not* in range 00080000 .. 000FFFFF
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*data_ptr = BX_MEM_THIS vector[a20addr];
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inc_one:
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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goto read_one;
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}
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// addr must be in range 000A0000 .. 000FFFFF
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// SMMRAM
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if (a20addr <= 0x000bffff) {
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// devices are not allowed to access SMMRAM under VGA memory
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if (cpu) *data_ptr = BX_MEM_THIS vector[a20addr];
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goto inc_one;
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}
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#if BX_SUPPORT_PCI
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if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
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{
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switch (DEV_pci_rd_memtype(a20addr)) {
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case 0x0: // Read from ROM
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if ((a20addr & 0xfffe0000) == 0x000e0000)
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{
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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}
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else
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{
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*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
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}
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goto inc_one;
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case 0x1: // Read from ShadowRAM
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*data_ptr = BX_MEM_THIS vector[a20addr];
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goto inc_one;
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default:
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BX_PANIC(("readPhysicalPage: default case"));
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}
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goto inc_one;
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}
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else
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#endif // #if BX_SUPPORT_PCI
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{
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if ((a20addr & 0xfffc0000) != 0x000c0000) {
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*data_ptr = BX_MEM_THIS vector[a20addr];
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}
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else if ((a20addr & 0xfffe0000) == 0x000e0000)
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{
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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}
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else
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{
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*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
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}
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goto inc_one;
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}
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}
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else
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{ // access outside limits of physical memory
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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for (unsigned i = 0; i < len; i++) {
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if (a20addr >= (bx_phy_address)~BIOS_MASK)
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*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
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else
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*data_ptr = 0xff;
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addr++;
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a20addr = (addr);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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}
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}
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}
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#endif // #if BX_PROVIDE_CPU_MEMORY
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