f9bd2b74be
2. Fixed bug [ 989478 ] I-Cache and undefined Instruktions The L4 microkernel uses an undefined instruction to trap for a special requests into the kernel (LOCK NOP). The handler fixes this up and gives the user a special code page with syscall stubs. If you're not using the I-Cache optimization everthing works find on bochs. But if you enable the I-Cache (--enable-icache), then the undefined opcode exception is thrown only once for ever virtual address it occurs. See the demodisk of the L4KA::pistachio (http://www.l4ka.org/projects/pistachio/download.php). In this case the pingpong benchmark of this demo is of interest. Everything runs fine until the program tries to spawn a new task for its measurements. This new task shares the code of the creating program. But the new task stops executing at the undefined instruction explained above and no exception is thrown.
173 lines
4.3 KiB
C++
Executable File
173 lines
4.3 KiB
C++
Executable File
/////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2004 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#include "softfloatx80.h"
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/* D9 C8 */
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void BX_CPU_C::FXCH_STi(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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int st0_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(0);
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int sti_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(i->rm());
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floatx80 st0_reg = BX_READ_FPU_REG(0);
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floatx80 sti_reg = BX_READ_FPU_REG(i->rm());
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clear_C1();
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if (st0_tag == FPU_Tag_Empty || sti_tag == FPU_Tag_Empty)
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{
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BX_CPU_THIS_PTR FPU_exception(FPU_EX_Stack_Underflow);
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if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
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{
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/* Masked response */
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if (st0_tag == FPU_Tag_Empty)
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{
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st0_reg = floatx80_default_nan;
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st0_tag = FPU_Tag_Special;
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}
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if (sti_tag == FPU_Tag_Empty)
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{
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sti_reg = floatx80_default_nan;
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sti_tag = FPU_Tag_Special;
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}
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}
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else return;
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}
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BX_WRITE_FPU_REGISTER_AND_TAG(st0_reg, st0_tag, i->rm());
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BX_WRITE_FPU_REGISTER_AND_TAG(sti_reg, sti_tag, 0);
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#else
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BX_INFO(("FXCH_STi: required FPU, configure --enable-fpu"));
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#endif
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}
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/* D9 E0 */
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void BX_CPU_C::FCHS(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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int st0_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(0);
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if (st0_tag == FPU_Tag_Empty)
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{
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BX_CPU_THIS_PTR FPU_stack_underflow(0);
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return;
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}
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clear_C1();
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floatx80 st0_reg = BX_READ_FPU_REG(0);
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BX_WRITE_FPU_REGISTER_AND_TAG(floatx80_chs(st0_reg), st0_tag, 0);
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#else
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BX_INFO(("FCHS: required FPU, configure --enable-fpu"));
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#endif
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}
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/* D9 E1 */
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void BX_CPU_C::FABS(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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int st0_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(0);
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if (st0_tag == FPU_Tag_Empty)
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{
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BX_CPU_THIS_PTR FPU_stack_underflow(0);
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return;
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}
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clear_C1();
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floatx80 st0_reg = BX_READ_FPU_REG(0);
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BX_WRITE_FPU_REGISTER_AND_TAG(floatx80_abs(st0_reg), st0_tag, 0);
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#else
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BX_INFO(("FABS: required FPU, configure --enable-fpu"));
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#endif
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}
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/* D9 F6 */
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void BX_CPU_C::FDECSTP(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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clear_C1();
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BX_CPU_THIS_PTR the_i387.tos = (BX_CPU_THIS_PTR the_i387.tos-1) & 7;
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#else
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BX_INFO(("FDECSTP: required FPU, configure --enable-fpu"));
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#endif
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}
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/* D9 F7 */
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void BX_CPU_C::FINCSTP(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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clear_C1();
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BX_CPU_THIS_PTR the_i387.tos = (BX_CPU_THIS_PTR the_i387.tos+1) & 7;
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#else
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BX_INFO(("FINCSTP: required FPU, configure --enable-fpu"));
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#endif
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}
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/* DD C0 */
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void BX_CPU_C::FFREE_STi(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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BX_CPU_THIS_PTR the_i387.FPU_settagi(FPU_Tag_Empty, i->rm());
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#else
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BX_INFO(("FFREE_STi: required FPU, configure --enable-fpu"));
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#endif
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}
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/*
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* Free the st(0) register and pop it from the FPU stack.
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* "Undocumented" by Intel & AMD but mentioned in AMDs Athlon Docs.
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*/
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/* DF C0 */
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void BX_CPU_C::FFREEP_STi(bxInstruction_c *i)
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{
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#if BX_SUPPORT_FPU
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BX_CPU_THIS_PTR prepareFPU(i);
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BX_CPU_THIS_PTR the_i387.FPU_settagi(FPU_Tag_Empty, i->rm());
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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#else
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BX_INFO(("FFREEP_STi: required FPU, configure --enable-fpu"));
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#endif
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}
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