44241a1e56
with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
381 lines
12 KiB
C
381 lines
12 KiB
C
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2003-2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_SSE_EXTENSIONS_H
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#define BX_SSE_EXTENSIONS_H
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/* XMM REGISTER */
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typedef union bx_xmm_reg_t {
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Bit8s xmm_sbyte[16];
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Bit16s xmm_s16[8];
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Bit32s xmm_s32[4];
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Bit64s xmm_s64[2];
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Bit8u xmm_ubyte[16];
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Bit16u xmm_u16[8];
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Bit32u xmm_u32[4];
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Bit64u xmm_u64[2];
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} BxPackedXmmRegister;
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#ifdef BX_BIG_ENDIAN
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#define xmm64s(i) xmm_s64[1 - (i)]
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#define xmm32s(i) xmm_s32[3 - (i)]
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#define xmm16s(i) xmm_s16[7 - (i)]
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#define xmmsbyte(i) xmm_sbyte[15 - (i)]
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#define xmmubyte(i) xmm_ubyte[15 - (i)]
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#define xmm16u(i) xmm_u16[7 - (i)]
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#define xmm32u(i) xmm_u32[3 - (i)]
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#define xmm64u(i) xmm_u64[1 - (i)]
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#else
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#define xmm64s(i) xmm_s64[(i)]
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#define xmm32s(i) xmm_s32[(i)]
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#define xmm16s(i) xmm_s16[(i)]
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#define xmmsbyte(i) xmm_sbyte[(i)]
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#define xmmubyte(i) xmm_ubyte[(i)]
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#define xmm16u(i) xmm_u16[(i)]
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#define xmm32u(i) xmm_u32[(i)]
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#define xmm64u(i) xmm_u64[(i)]
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#endif
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/* AVX REGISTER */
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enum bx_avx_vector_length {
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BX_NO_VL,
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BX_VL128,
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BX_VL256
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};
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#if BX_SUPPORT_AVX
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#define BX_VLMAX BX_VL256
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#else
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#define BX_VLMAX BX_VL128
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#endif
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#if BX_SUPPORT_AVX
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typedef union bx_avx_reg_t {
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Bit8s avx_sbyte[32];
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Bit16s avx_s16[16];
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Bit32s avx_s32[8];
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Bit64s avx_s64[4];
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Bit8u avx_ubyte[32];
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Bit16u avx_u16[16];
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Bit32u avx_u32[8];
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Bit64u avx_u64[4];
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BxPackedXmmRegister avx_v128[2];
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} BxPackedAvxRegister;
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#ifdef BX_BIG_ENDIAN
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#define avx64s(i) avx_s64[3 - (i)]
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#define avx32s(i) avx_s32[7 - (i)]
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#define avx16s(i) avx_s16[15 - (i)]
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#define avxsbyte(i) avx_sbyte[31 - (i)]
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#define avxubyte(i) avx_ubyte[31 - (i)]
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#define avx16u(i) avx_u16[15 - (i)]
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#define avx32u(i) avx_u32[7 - (i)]
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#define avx64u(i) avx_u64[3 - (i)]
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#define avx128(i) avx_v128[1 - (i)]
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#else
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#define avx64s(i) avx_s64[(i)]
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#define avx32s(i) avx_s32[(i)]
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#define avx16s(i) avx_s16[(i)]
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#define avxsbyte(i) avx_sbyte[(i)]
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#define avxubyte(i) avx_ubyte[(i)]
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#define avx16u(i) avx_u16[(i)]
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#define avx32u(i) avx_u32[(i)]
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#define avx64u(i) avx_u64[(i)]
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#define avx128(i) avx_v128[(i)]
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#endif
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#endif
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#if BX_SUPPORT_X86_64
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# define BX_XMM_REGISTERS 16
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#else
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# define BX_XMM_REGISTERS 8
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#endif
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#if BX_SUPPORT_AVX
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/* read XMM register */
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#define BX_READ_XMM_REG(index) ((BX_CPU_THIS_PTR vmm[index]).avx128(0))
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#else
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/* read XMM register */
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#define BX_READ_XMM_REG(index) ((BX_CPU_THIS_PTR vmm[index]))
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#endif
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/* read only high 64 bit of the register */
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#define BX_READ_XMM_REG_HI_QWORD(index) \
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((BX_READ_XMM_REG(index)).xmm64u(1))
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/* read only low 64 bit of the register */
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#define BX_READ_XMM_REG_LO_QWORD(index) \
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((BX_READ_XMM_REG(index)).xmm64u(0))
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/* read only low 32 bit of the register */
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#define BX_READ_XMM_REG_LO_DWORD(index) \
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((BX_READ_XMM_REG(index)).xmm32u(0))
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/* read only low 16 bit of the register */
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#define BX_READ_XMM_REG_LO_WORD(index) \
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((BX_READ_XMM_REG(index)).xmm16u(0))
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/* read only low 8 bit of the register */
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#define BX_READ_XMM_REG_LO_BYTE(index) \
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((BX_READ_XMM_REG(index)).xmmubyte(0))
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/* short names for above macroses */
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#define BX_XMM_REG_HI_QWORD BX_READ_XMM_REG_HI_QWORD
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#define BX_XMM_REG_LO_QWORD BX_READ_XMM_REG_LO_QWORD
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#define BX_XMM_REG_LO_DWORD BX_READ_XMM_REG_LO_DWORD
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#define BX_XMM_REG BX_READ_XMM_REG
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/* store only high 64 bit of the register, rest of the register unchanged */
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#define BX_WRITE_XMM_REG_HI_QWORD(index, reg64) \
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{ (BX_XMM_REG(index)).xmm64u(1) = (reg64); }
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/* store only low 64 bit of the register, rest of the register unchanged */
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#define BX_WRITE_XMM_REG_LO_QWORD(index, reg64) \
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{ (BX_XMM_REG(index)).xmm64u(0) = (reg64); }
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/* store only low 32 bit of the register, rest of the register unchanged */
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#define BX_WRITE_XMM_REG_LO_DWORD(index, reg32) \
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{ (BX_XMM_REG(index)).xmm32u(0) = (reg32); }
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/* store only low 16 bit of the register, rest of the register unchanged */
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#define BX_WRITE_XMM_REG_LO_WORD(index, reg16) \
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{ (BX_XMM_REG(index)).xmm16u(0) = (reg16); }
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/* store only low 8 bit of the register, rest of the register unchanged */
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#define BX_WRITE_XMM_REG_LO_BYTE(index, reg8) \
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{ (BX_XMM_REG(index)).xmmubyte(0) = (reg8); }
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/* store XMM register */
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#define BX_WRITE_XMM_REG(index, reg) \
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{ (BX_XMM_REG(index)) = (reg); }
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#if BX_SUPPORT_AVX
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/* read AVX register */
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#define BX_READ_AVX_REG(index) (BX_CPU_THIS_PTR vmm[index])
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#define BX_AVX_REG BX_READ_AVX_REG
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/* read AVX register */
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#define BX_READ_AVX_REG_LINE(index, line) \
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((BX_READ_AVX_REG(index)).avx128(line))
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/* write AVX register */
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#define BX_WRITE_AVX_REG(index, reg) \
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{ (BX_READ_AVX_REG(index)) = (reg); }
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/* clear upper part of AVX register */
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#define BX_CLEAR_AVX_HIGH(index) \
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{ (BX_READ_AVX_REG(index)).avx64u(2) = (BX_READ_AVX_REG(index)).avx64u(3) = 0; }
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/* write AVX register and potentialy clear upper part of the register */
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#define BX_WRITE_AVX_REGZ(index, reg, vlen) \
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{ BX_CPU_THIS_PTR vmm[index] = (reg); \
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if (vlen == BX_VL128) BX_CLEAR_AVX_HIGH(index); }
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/* write XMM register while clearing upper part of AVX register */
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#define BX_WRITE_XMM_REG_CLEAR_HIGH(index, reg) \
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{ BX_XMM_REG(index) = (reg); BX_CLEAR_AVX_HIGH(index); }
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/* write XMM register while clearing upper part of AVX register */
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#define BX_WRITE_XMM_REGZ(index, reg, vlen) \
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{ (BX_XMM_REG(index)) = (reg); \
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if (vlen == BX_VL128) BX_CLEAR_AVX_HIGH(index); }
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#else
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/* write XMM register while clearing upper part of AVX register */
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#define BX_WRITE_XMM_REG_CLEAR_HIGH(index, reg) \
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BX_WRITE_XMM_REG(index, reg)
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/* write XMM register while clearing upper part of AVX register */
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#define BX_WRITE_XMM_REGZ(index, reg, vlen) \
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BX_WRITE_XMM_REG(index, reg)
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#endif
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/* MXCSR REGISTER */
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/* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16
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* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|== (reserved)
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* 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0|MM| 0
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*
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* 15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
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* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|==
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* FZ| R C |PM|UM|OM|ZM|DM|IM|DZ|PE|UE|OE|ZE|DE|IE
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*/
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/* MXCSR REGISTER FIELDS DESCRIPTION */
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/*
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* IE 0 Invalid-Operation Exception 0
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* DE 1 Denormalized-Operand Exception 0
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* ZE 2 Zero-Divide Exception 0
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* OE 3 Overflow Exception 0
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* UE 4 Underflow Exception 0
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* PE 5 Precision Exception 0
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* DZ 6 Denormals are Zeros 0
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* IM 7 Invalid-Operation Exception Mask 1
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* DM 8 Denormalized-Operand Exception Mask 1
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* ZM 9 Zero-Divide Exception Mask 1
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* OM 10 Overflow Exception Mask 1
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* UM 11 Underflow Exception Mask 1
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* PM 12 Precision Exception Mask 1
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* RC 13-14 Floating-Point Rounding Control 00
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* FZ 15 Flush-to-Zero for Masked Underflow 0
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* RZ 16 Reserved 0
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* MM 17 Misaligned Exception Mask 0
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*/
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#define MXCSR_EXCEPTIONS 0x0000003F
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#define MXCSR_DAZ 0x00000040
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#define MXCSR_MASKED_EXCEPTIONS 0x00001F80
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#define MXCSR_ROUNDING_CONTROL 0x00006000
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#define MXCSR_FLUSH_MASKED_UNDERFLOW 0x00008000
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#define MXCSR_MISALIGNED_EXCEPTION_MASK 0x00020000
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#define MXCSR_IE 0x00000001
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#define MXCSR_DE 0x00000002
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#define MXCSR_ZE 0x00000004
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#define MXCSR_OE 0x00000008
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#define MXCSR_UE 0x00000010
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#define MXCSR_PE 0x00000020
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#define MXCSR_IM 0x00000080
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#define MXCSR_DM 0x00000100
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#define MXCSR_ZM 0x00000200
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#define MXCSR_OM 0x00000400
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#define MXCSR_UM 0x00000800
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#define MXCSR_PM 0x00001000
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#define MXCSR_RESET 0x00001F80 /* reset value of the MXCSR register */
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struct BOCHSAPI bx_mxcsr_t
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{
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Bit32u mxcsr;
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bx_mxcsr_t (Bit32u val = MXCSR_RESET)
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: mxcsr(val) {}
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#define IMPLEMENT_MXCSR_ACCESSOR(name, bitmask, bitnum) \
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int get_##name () const { \
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return (mxcsr & (bitmask)) >> (bitnum); \
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}
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IMPLEMENT_MXCSR_ACCESSOR(exceptions_masks, MXCSR_MASKED_EXCEPTIONS, 7);
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IMPLEMENT_MXCSR_ACCESSOR(DAZ, MXCSR_DAZ, 6);
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IMPLEMENT_MXCSR_ACCESSOR(rounding_mode, MXCSR_ROUNDING_CONTROL, 13);
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IMPLEMENT_MXCSR_ACCESSOR(flush_masked_underflow, MXCSR_FLUSH_MASKED_UNDERFLOW, 15);
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IMPLEMENT_MXCSR_ACCESSOR(MM, MXCSR_MISALIGNED_EXCEPTION_MASK, 17);
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IMPLEMENT_MXCSR_ACCESSOR(IE, MXCSR_IE, 0);
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IMPLEMENT_MXCSR_ACCESSOR(DE, MXCSR_DE, 1);
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IMPLEMENT_MXCSR_ACCESSOR(ZE, MXCSR_ZE, 2);
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IMPLEMENT_MXCSR_ACCESSOR(OE, MXCSR_OE, 3);
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IMPLEMENT_MXCSR_ACCESSOR(UE, MXCSR_UE, 4);
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IMPLEMENT_MXCSR_ACCESSOR(PE, MXCSR_PE, 5);
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IMPLEMENT_MXCSR_ACCESSOR(IM, MXCSR_IM, 7);
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IMPLEMENT_MXCSR_ACCESSOR(DM, MXCSR_DM, 8);
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IMPLEMENT_MXCSR_ACCESSOR(ZM, MXCSR_ZM, 9);
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IMPLEMENT_MXCSR_ACCESSOR(OM, MXCSR_OM, 10);
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IMPLEMENT_MXCSR_ACCESSOR(UM, MXCSR_UM, 11);
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IMPLEMENT_MXCSR_ACCESSOR(PM, MXCSR_PM, 12);
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void set_exceptions(int status) {
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mxcsr |= (status & MXCSR_EXCEPTIONS);
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}
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};
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#if defined(NEED_CPU_REG_SHORTCUTS)
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#define MXCSR (BX_CPU_THIS_PTR mxcsr)
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#define BX_MXCSR_REGISTER (BX_CPU_THIS_PTR mxcsr.mxcsr)
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#define MXCSR_MASK (BX_CPU_THIS_PTR mxcsr_mask)
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#endif
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/* INTEGER SATURATION */
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/*
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* SaturateWordSToByteS converts a signed 16-bit value to a signed
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* 8-bit value. If the signed 16-bit value is less than -128, it is
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* represented by the saturated value -128 (0x80). If it is greater
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* than 127, it is represented by the saturated value 127 (0x7F).
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*/
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BX_CPP_INLINE Bit8s BX_CPP_AttrRegparmN(1) SaturateWordSToByteS(Bit16s value)
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{
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if(value < -128) return -128;
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if(value > 127) return 127;
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return (Bit8s) value;
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}
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/*
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* SaturateDwordSToWordS converts a signed 32-bit value to a signed
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* 16-bit value. If the signed 32-bit value is less than -32768, it is
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* represented by the saturated value -32768 (0x8000). If it is greater
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* than 32767, it is represented by the saturated value 32767 (0x7FFF).
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*/
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BX_CPP_INLINE Bit16s BX_CPP_AttrRegparmN(1) SaturateDwordSToWordS(Bit32s value)
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{
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if(value < -32768) return -32768;
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if(value > 32767) return 32767;
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return (Bit16s) value;
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}
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/*
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* SaturateWordSToByteU converts a signed 16-bit value to an unsigned
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* 8-bit value. If the signed 16-bit value is less than zero it is
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* represented by the saturated value zero (0x00).If it is greater than
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* 255 it is represented by the saturated value 255 (0xFF).
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*/
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BX_CPP_INLINE Bit8u BX_CPP_AttrRegparmN(1) SaturateWordSToByteU(Bit16s value)
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{
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if(value < 0) return 0;
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if(value > 255) return 255;
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return (Bit8u) value;
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}
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/*
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* SaturateDwordSToWordU converts a signed 32-bit value to an unsigned
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* 16-bit value. If the signed 32-bit value is less than zero, it is
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* represented by the saturated value zero (0x0000). If it is greater
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* than 65535, it is represented by the saturated value 65535 (0xFFFF).
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*/
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BX_CPP_INLINE Bit16u BX_CPP_AttrRegparmN(1) SaturateDwordSToWordU(Bit32s value)
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{
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if(value < 0) return 0;
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if(value > 65535) return 65535;
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return (Bit16u) value;
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}
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#endif
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