d11114ac19
The patch was posted in mailing list at Thu 6/16/2011.
Desription for CHANGES:
- Memory
- Added new configure option which enables RAM file backing for large guest
memory with a smaller amount host memory, without causing a panic when
host memory is exhausted (patch by Gary Cameron). To enable configure with
--enable-large-ramfile option.
1806 lines
63 KiB
C++
1806 lines
63 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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// X86 Registers Which Affect Paging:
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// ==================================
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//
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// CR0:
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// bit 31: PG, Paging (386+)
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// bit 16: WP, Write Protect (486+)
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// 0: allow supervisor level writes into user level RO pages
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// 1: inhibit supervisor level writes into user level RO pages
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//
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// CR3:
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// bit 31..12: PDBR, Page Directory Base Register (386+)
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// bit 4: PCD, Page level Cache Disable (486+)
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// Controls caching of current page directory. Affects only the processor's
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// internal caches (L1 and L2).
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// This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
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// Values:
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// 0: Page Directory can be cached
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// 1: Page Directory not cached
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// bit 3: PWT, Page level Writes Transparent (486+)
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// Controls write-through or write-back caching policy of current page
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// directory. Affects only the processor's internal caches (L1 and L2).
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// This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
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// Values:
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// 0: write-back caching enabled
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// 1: write-through caching enabled
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//
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// CR4:
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// bit 4: PSE, Page Size Extension (Pentium+)
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// 0: 4KByte pages (typical)
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// 1: 4MByte or 2MByte pages
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// bit 5: PAE, Physical Address Extension (Pentium Pro+)
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// 0: 32bit physical addresses
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// 1: 36bit physical addresses
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// bit 7: PGE, Page Global Enable (Pentium Pro+)
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// The global page feature allows frequently used or shared pages
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// to be marked as global (PDE or PTE bit 8). Global pages are
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// not flushed from TLB on a task switch or write to CR3.
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// Values:
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// 0: disables global page feature
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// 1: enables global page feature
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//
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// page size extention and physical address size extention matrix (legacy mode)
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// ==============================================================================
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// CR0.PG CR4.PAE CR4.PSE PDPE.PS PDE.PS | page size physical address size
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// ==============================================================================
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// 0 X X R X | -- paging disabled
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// 1 0 0 R X | 4K 32bits
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// 1 0 1 R 0 | 4K 32bits
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// 1 0 1 R 1 | 4M 32bits
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// 1 1 X R 0 | 4K 36bits
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// 1 1 X R 1 | 2M 36bits
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// page size extention and physical address size extention matrix (long mode)
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// ==============================================================================
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// CR0.PG CR4.PAE CR4.PSE PDPE.PS PDE.PS | page size physical address size
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// ==============================================================================
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// 1 1 X 0 0 | 4K 52bits
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// 1 1 X 0 1 | 2M 52bits
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// 1 1 X 1 - | 1G 52bits
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// Page Directory/Table Entry Fields Defined:
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// ==========================================
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// NX: No Execute
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// This bit controls the ability to execute code from all physical
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// pages mapped by the table entry.
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// 0: Code can be executed from the mapped physical pages
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// 1: Code cannot be executed
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// The NX bit can only be set when the no-execute page-protection
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// feature is enabled by setting EFER.NXE=1, If EFER.NXE=0, the
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// NX bit is treated as reserved. In this case, #PF occurs if the
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// NX bit is not cleared to zero.
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//
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// G: Global flag
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// Indiciates a global page when set. When a page is marked
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// global and the PGE flag in CR4 is set, the page table or
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// directory entry for the page is not invalidated in the TLB
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// when CR3 is loaded or a task switch occurs. Only software
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// clears and sets this flag. For page directory entries that
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// point to page tables, this flag is ignored and the global
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// characteristics of a page are set in the page table entries.
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//
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// PS: Page Size flag
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// Only used in page directory entries. When PS=0, the page
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// size is 4KBytes and the page directory entry points to a
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// page table. When PS=1, the page size is 4MBytes for
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// normal 32-bit addressing and 2MBytes if extended physical
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// addressing.
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//
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// PAT: Page-Attribute Table
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// This bit is only present in the lowest level of the page
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// translation hierarchy. The PAT bit is the high-order bit
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// of a 3-bit index into the PAT register. The other two
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// bits involved in forming the index are the PCD and PWT
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// bits.
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//
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// D: Dirty bit:
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// Processor sets the Dirty bit in the 2nd-level page table before a
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// write operation to an address mapped by that page table entry.
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// Dirty bit in directory entries is undefined.
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//
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// A: Accessed bit:
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// Processor sets the Accessed bits in both levels of page tables before
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// a read/write operation to a page.
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//
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// PCD: Page level Cache Disable
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// Controls caching of individual pages or page tables.
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// This allows a per-page based mechanism to disable caching, for
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// those pages which contained memory mapped IO, or otherwise
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// should not be cached. Processor ignores this flag if paging
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// is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
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// Values:
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// 0: page or page table can be cached
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// 1: page or page table is not cached (prevented)
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//
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// PWT: Page level Write Through
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// Controls the write-through or write-back caching policy of individual
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// pages or page tables. Processor ignores this flag if paging
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// is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
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// Values:
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// 0: write-back caching
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// 1: write-through caching
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//
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// U/S: User/Supervisor level
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// 0: Supervisor level - for the OS, drivers, etc.
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// 1: User level - application code and data
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//
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// R/W: Read/Write access
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// 0: read-only access
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// 1: read/write access
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//
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// P: Present
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// 0: Not present
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// 1: Present
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// ==========================================
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// Combined page directory/page table protection:
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// ==============================================
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// There is one column for the combined effect on a 386
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// and one column for the combined effect on a 486+ CPU.
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//
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// +----------------+-----------------+----------------+----------------+
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// | Page Directory| Page Table | Combined 386 | Combined 486+ |
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// |Privilege Type | Privilege Type | Privilege Type| Privilege Type|
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// |----------------+-----------------+----------------+----------------|
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// |User R | User R | User R | User R |
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// |User R | User RW | User R | User R |
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// |User RW | User R | User R | User R |
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// |User RW | User RW | User RW | User RW |
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// |User R | Supervisor R | User R | Supervisor RW |
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// |User R | Supervisor RW | User R | Supervisor RW |
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// |User RW | Supervisor R | User R | Supervisor RW |
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// |User RW | Supervisor RW | User RW | Supervisor RW |
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// |Supervisor R | User R | User R | Supervisor RW |
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// |Supervisor R | User RW | User R | Supervisor RW |
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// |Supervisor RW | User R | User R | Supervisor RW |
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// |Supervisor RW | User RW | User RW | Supervisor RW |
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// |Supervisor R | Supervisor R | Supervisor RW | Supervisor RW |
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// |Supervisor R | Supervisor RW | Supervisor RW | Supervisor RW |
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// |Supervisor RW | Supervisor R | Supervisor RW | Supervisor RW |
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// |Supervisor RW | Supervisor RW | Supervisor RW | Supervisor RW |
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// +----------------+-----------------+----------------+----------------+
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// Page Fault Error Code Format:
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// =============================
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//
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// bits 31..4: Reserved
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// bit 3: RSVD (Pentium Pro+)
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// 0: fault caused by reserved bits set to 1 in a page directory
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// when the PSE or PAE flags in CR4 are set to 1
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// 1: fault was not caused by reserved bit violation
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// bit 2: U/S (386+)
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// 0: fault originated when in supervior mode
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// 1: fault originated when in user mode
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// bit 1: R/W (386+)
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// 0: access causing the fault was a read
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// 1: access causing the fault was a write
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// bit 0: P (386+)
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// 0: fault caused by a nonpresent page
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// 1: fault caused by a page level protection violation
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// Some paging related notes:
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// ==========================
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//
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// - When the processor is running in supervisor level, all pages are both
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// readable and writable (write-protect ignored). When running at user
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// level, only pages which belong to the user level are accessible;
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// read/write & read-only are readable, read/write are writable.
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//
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// - If the Present bit is 0 in either level of page table, an
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// access which uses these entries will generate a page fault.
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//
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// - (A)ccess bit is used to report read or write access to a page
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// or 2nd level page table.
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//
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// - (D)irty bit is used to report write access to a page.
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//
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// - Processor running at CPL=0,1,2 maps to U/S=0
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// Processor running at CPL=3 maps to U/S=1
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#if BX_SUPPORT_X86_64
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#define BX_INVALID_TLB_ENTRY BX_CONST64(0xffffffffffffffff)
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#else
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#define BX_INVALID_TLB_ENTRY 0xffffffff
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#endif
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// bit [11] of the TLB lpf used for TLB_HostPtr valid indication
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#define TLB_LPFOf(laddr) AlignedAccessLPFOf(laddr, 0x7ff)
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#if BX_CPU_LEVEL >= 4
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# define BX_PRIV_CHECK_SIZE 32
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#else
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# define BX_PRIV_CHECK_SIZE 16
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#endif
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// The 'priv_check' array is used to decide if the current access
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// has the proper paging permissions. An index is formed, based
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// on parameters such as the access type and level, the write protect
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// flag and values cached in the TLB. The format of the index into this
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// array is:
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//
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// |4 |3 |2 |1 |0 |
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// |wp|us|us|rw|rw|
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// | | | | |
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// | | | | +---> r/w of current access
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// | | +--+------> u/s,r/w combined of page dir & table (cached)
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// | +------------> u/s of current access
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// +---------------> Current CR0.WP value
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/* 0xff0bbb0b */
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static const Bit8u priv_check[BX_PRIV_CHECK_SIZE] =
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{
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1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1,
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#if BX_CPU_LEVEL >= 4
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1, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1
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#endif
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};
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#define BX_PAGING_PHY_ADDRESS_RESERVED_BITS \
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(BX_PHY_ADDRESS_RESERVED_BITS & BX_CONST64(0xfffffffffffff))
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#define PAGE_DIRECTORY_NX_BIT (BX_CONST64(0x8000000000000000))
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#define BX_CR3_PAGING_MASK (BX_CONST64(0x000ffffffffff000))
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#define BX_CR3_LEGACY_PAE_PAGING_MASK (0xffffffe0)
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// Each entry in the TLB cache has 3 entries:
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//
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// lpf: Linear Page Frame (page aligned linear address of page)
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// bits 32..12 Linear page frame
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// bit 11 0: TLB HostPtr access allowed, 1: not allowed
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// bit 10...0 Invalidate index
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//
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// ppf: Physical Page Frame (page aligned phy address of page)
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//
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// hostPageAddr:
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// Host Page Frame address used for direct access to
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// the mem.vector[] space allocated for the guest physical
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// memory. If this is zero, it means that a pointer
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// to the host space could not be generated, likely because
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// that page of memory is not standard memory (it might
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// be memory mapped IO, ROM, etc).
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//
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// accessBits:
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//
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// bit 31: Page is a global page.
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//
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// The following bits are used for a very efficient permissions
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// check. The goal is to be able, using only the current privilege
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// level and access type, to determine if the page tables allow the
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// access to occur or at least should rewalk the page tables. On
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// the first read access, permissions are set to only read, so a
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// rewalk is necessary when a subsequent write fails the tests.
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// This allows for the dirty bit to be set properly, but for the
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// test to be efficient. Note that the CR0.WP flag is not present.
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// The values in the following flags is based on the current CR0.WP
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// value, necessitating a TLB flush when CR0.WP changes.
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//
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// The test is:
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// OK = (accessBits & ((E<<2) | (W<<1) | U)) <> 0
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//
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// where E:1=Execute, 0=Data;
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// W:1=Write, 0=Read;
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// U:1=CPL3, 0=CPL0-2
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//
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// Thus for reads, it is:
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// OK = ( U )
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// for writes:
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// OK = 0x2 | ( U )
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// and for code fetches:
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// OK = 0x4 | ( U )
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//
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// Note, that the TLB should have TLB_HostPtr bit set when direct
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// access through host pointer is NOT allowed for the page. A memory
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// operation asking for a direct access through host pointer will
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// set TLB_HostPtr bit in its lpf field and thus get TLB miss result
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// when the direct access is not allowed.
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//
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#define TLB_HostPtr (0x800) /* set this bit when direct access is NOT allowed */
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#define TLB_GlobalPage (0x80000000)
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#define TLB_SysOnly (0x1)
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#define TLB_ReadOnly (0x2)
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#define TLB_NoExecute (0x4)
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// === TLB Instrumentation section ==============================
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// Note: this is an approximation of what Peter Tattam had.
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#define InstrumentTLB 0
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#if InstrumentTLB
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static unsigned tlbLookups=0;
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static unsigned tlbMisses=0;
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static unsigned tlbGlobalFlushes=0;
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static unsigned tlbNonGlobalFlushes=0;
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#define InstrTLB_StatsMask 0xfffff
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#define InstrTLB_Stats() {\
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if ((tlbLookups & InstrTLB_StatsMask) == 0) { \
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BX_INFO(("TLB lookup:%8d miss:%8d %6.2f%% flush:%8d %6.2f%%", \
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tlbLookups, \
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tlbMisses, \
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tlbMisses * 100.0 / tlbLookups, \
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(tlbGlobalFlushes+tlbNonGlobalFlushes), \
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(tlbGlobalFlushes+tlbNonGlobalFlushes) * 100.0 / tlbLookups \
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)); \
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tlbLookups = tlbMisses = tlbGlobalFlushes = tlbNonGlobalFlushes = 0; \
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} \
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}
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#define InstrTLB_Increment(v) (v)++
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#else
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#define InstrTLB_Stats()
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#define InstrTLB_Increment(v)
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#endif
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// ==============================================================
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void BX_CPU_C::TLB_flush(void)
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{
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#if InstrumentTLB
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InstrTLB_Increment(tlbGlobalFlushes);
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#endif
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invalidate_prefetch_q();
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for (unsigned n=0; n<BX_TLB_SIZE; n++) {
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BX_CPU_THIS_PTR TLB.entry[n].lpf = BX_INVALID_TLB_ENTRY;
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}
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#if BX_CPU_LEVEL >= 5
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BX_CPU_THIS_PTR TLB.split_large = 0; // flush whole TLB
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#endif
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#if BX_SUPPORT_MONITOR_MWAIT
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// invalidating of the TLB might change translation for monitored page
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// and cause subsequent MWAIT instruction to wait forever
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BX_CPU_THIS_PTR monitor.reset_monitor();
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#endif
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}
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#if BX_CPU_LEVEL >= 6
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void BX_CPU_C::TLB_flushNonGlobal(void)
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{
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#if InstrumentTLB
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InstrTLB_Increment(tlbNonGlobalFlushes);
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#endif
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invalidate_prefetch_q();
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BX_CPU_THIS_PTR TLB.split_large = 0;
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for (unsigned n=0; n<BX_TLB_SIZE; n++) {
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[n];
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if (!(tlbEntry->accessBits & TLB_GlobalPage)) {
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tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
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}
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else {
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if (tlbEntry->lpf_mask > 0xfff)
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BX_CPU_THIS_PTR TLB.split_large = 1;
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}
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}
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#if BX_SUPPORT_MONITOR_MWAIT
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// invalidating of the TLB might change translation for monitored page
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// and cause subsequent MWAIT instruction to wait forever
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BX_CPU_THIS_PTR monitor.reset_monitor();
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#endif
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}
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#endif
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void BX_CPU_C::TLB_invlpg(bx_address laddr)
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{
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invalidate_prefetch_q();
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BX_DEBUG(("TLB_invlpg(0x"FMT_ADDRX"): invalidate TLB entry", laddr));
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#if BX_CPU_LEVEL >= 5
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bx_bool large = 0;
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if (BX_CPU_THIS_PTR TLB.split_large) {
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// make sure INVLPG handles correctly large pages
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for (unsigned n=0; n<BX_TLB_SIZE; n++) {
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[n];
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bx_address lpf_mask = tlbEntry->lpf_mask;
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if ((laddr & ~lpf_mask) == (tlbEntry->lpf & ~lpf_mask)) {
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tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
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}
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else {
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if (lpf_mask > 0xfff) large = 1;
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}
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}
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BX_CPU_THIS_PTR TLB.split_large = large;
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}
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else
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#endif
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{
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unsigned TLB_index = BX_TLB_INDEX_OF(laddr, 0);
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bx_address lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
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if (TLB_LPFOf(tlbEntry->lpf) == lpf) {
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tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
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}
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}
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#if BX_SUPPORT_MONITOR_MWAIT
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// invalidating of the TLB entry might change translation for monitored
|
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// page and cause subsequent MWAIT instruction to wait forever
|
|
BX_CPU_THIS_PTR monitor.reset_monitor();
|
|
#endif
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
|
|
{
|
|
if (!real_mode() && CPL!=0) {
|
|
BX_ERROR(("INVLPG: priveledge check failed, generate #GP(0)"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
bx_address laddr = get_laddr(i->seg(), eaddr);
|
|
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_INVLPG(i, laddr);
|
|
#endif
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (IsCanonical(laddr))
|
|
#endif
|
|
{
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_INVLPG, laddr);
|
|
TLB_invlpg(laddr);
|
|
}
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
// error checking order - page not present, reserved bits, protection
|
|
#define ERROR_NOT_PRESENT 0x00
|
|
#define ERROR_PROTECTION 0x01
|
|
#define ERROR_RESERVED 0x08
|
|
#define ERROR_CODE_ACCESS 0x10
|
|
|
|
void BX_CPU_C::page_fault(unsigned fault, bx_address laddr, unsigned user, unsigned rw)
|
|
{
|
|
unsigned error_code = fault;
|
|
unsigned isWrite = rw & 1;
|
|
|
|
error_code |= (user << 2) | (isWrite << 1);
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (rw == BX_EXECUTE) {
|
|
if (BX_CPU_THIS_PTR cr4.get_SMEP())
|
|
error_code |= ERROR_CODE_ACCESS; // I/D = 1
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE() && BX_CPU_THIS_PTR efer.get_NXE())
|
|
error_code |= ERROR_CODE_ACCESS;
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_Event(0, BX_HARDWARE_EXCEPTION, BX_PF_EXCEPTION, error_code, 1, laddr); // before the CR2 was modified
|
|
#endif
|
|
|
|
BX_CPU_THIS_PTR cr2 = laddr;
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
BX_DEBUG(("page fault for address %08x%08x @ %08x%08x",
|
|
GET32H(laddr), GET32L(laddr), GET32H(RIP), GET32L(RIP)));
|
|
#else
|
|
BX_DEBUG(("page fault for address %08x @ %08x", laddr, EIP));
|
|
#endif
|
|
|
|
exception(BX_PF_EXCEPTION, error_code);
|
|
}
|
|
|
|
#define BX_LEVEL_PML4 3
|
|
#define BX_LEVEL_PDPE 2
|
|
#define BX_LEVEL_PDE 1
|
|
#define BX_LEVEL_PTE 0
|
|
|
|
#if BX_SUPPORT_X86_64 || BX_DEBUGGER
|
|
static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" };
|
|
#endif
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
int BX_CPU_C::check_entry_PAE(const char *s, Bit64u entry, Bit64u reserved, unsigned rw, bx_bool *nx_fault)
|
|
{
|
|
if (!(entry & 0x1)) {
|
|
BX_DEBUG(("%s: entry not present", s));
|
|
return ERROR_NOT_PRESENT;
|
|
}
|
|
|
|
if (entry & reserved) {
|
|
BX_DEBUG(("%s: reserved bit is set %08x:%08x", s, GET32H(entry), GET32L(entry)));
|
|
return ERROR_RESERVED | ERROR_PROTECTION;
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (! long_mode()) {
|
|
if (entry & BX_CONST64(0x7ff0000000000000)) {
|
|
BX_DEBUG(("%s: reserved bit is set %08x:%08x", s, GET32H(entry), GET32L(entry)));
|
|
return ERROR_RESERVED | ERROR_PROTECTION;
|
|
}
|
|
}
|
|
|
|
if (entry & PAGE_DIRECTORY_NX_BIT) {
|
|
if (! BX_CPU_THIS_PTR efer.get_NXE()) {
|
|
BX_DEBUG(("%s: NX bit set when EFER.NXE is disabled", s));
|
|
return ERROR_RESERVED | ERROR_PROTECTION;
|
|
}
|
|
if (rw == BX_EXECUTE) {
|
|
BX_DEBUG(("%s: non-executable page fault occured", s));
|
|
*nx_fault = 1;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return -1;
|
|
}
|
|
|
|
// Format of a Long Mode Non-Leaf Entry
|
|
// -----------------------------------------------------------
|
|
// 00 | Present (P)
|
|
// 01 | R/W
|
|
// 02 | U/S
|
|
// 03 | Page-Level Write-Through (PWT)
|
|
// 04 | Page-Level Cache-Disable (PCD)
|
|
// 05 | Accessed (A)
|
|
// 06 | (ignored)
|
|
// 07 | Page Size (PS), must be 0 if no Large Page on the level
|
|
// 11-08 | (ignored)
|
|
// PA-12 | Physical address of 4-KByte aligned page-directory-pointer table
|
|
// 51-PA | Reserved (must be zero)
|
|
// 62-52 | (ignored)
|
|
// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
|
|
// -----------------------------------------------------------
|
|
|
|
#define PAGING_PAE_RESERVED_BITS (BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
|
|
|
|
// Format of a PDPTE that References a 1-GByte Page
|
|
// -----------------------------------------------------------
|
|
// 00 | Present (P)
|
|
// 01 | R/W
|
|
// 02 | U/S
|
|
// 03 | Page-Level Write-Through (PWT)
|
|
// 04 | Page-Level Cache-Disable (PCD)
|
|
// 05 | Accessed (A)
|
|
// 06 | (ignored)
|
|
// 07 | Page Size, must be 1 to indicate a 1-GByte Page
|
|
// 08 | Global (G) (if CR4.PGE=1, ignored otherwise)
|
|
// 11-09 | (ignored)
|
|
// 12 | PAT (if PAT is supported, reserved otherwise)
|
|
// 29-13 | Reserved (must be zero)
|
|
// PA-30 | Physical address of the 1-Gbyte Page
|
|
// 51-PA | Reserved (must be zero)
|
|
// 62-52 | (ignored)
|
|
// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
|
|
// -----------------------------------------------------------
|
|
|
|
#define PAGING_PAE_PDPTE1G_RESERVED_BITS \
|
|
(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x3FFFE000))
|
|
|
|
// Format of a PAE PDE that Maps a 2-MByte Page
|
|
// -----------------------------------------------------------
|
|
// 00 | Present (P)
|
|
// 01 | R/W
|
|
// 02 | U/S
|
|
// 03 | Page-Level Write-Through (PWT)
|
|
// 04 | Page-Level Cache-Disable (PCD)
|
|
// 05 | Accessed (A)
|
|
// 06 | Dirty (D)
|
|
// 07 | Page Size (PS), must be 1 to indicate a 2-MByte Page
|
|
// 08 | Global (G) (if CR4.PGE=1, ignored otherwise)
|
|
// 11-09 | (ignored)
|
|
// 12 | PAT (if PAT is supported, reserved otherwise)
|
|
// 20-13 | Reserved (must be zero)
|
|
// PA-21 | Physical address of the 2-MByte page
|
|
// 51-PA | Reserved (must be zero)
|
|
// 62-52 | ignored in long mode, reserved (must be 0) in legacy PAE mode
|
|
// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
|
|
// -----------------------------------------------------------
|
|
|
|
#define PAGING_PAE_PDE2M_RESERVED_BITS \
|
|
(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x001FE000))
|
|
|
|
// Format of a PAE PTE that Maps a 4-KByte Page
|
|
// -----------------------------------------------------------
|
|
// 00 | Present (P)
|
|
// 01 | R/W
|
|
// 02 | U/S
|
|
// 03 | Page-Level Write-Through (PWT)
|
|
// 04 | Page-Level Cache-Disable (PCD)
|
|
// 05 | Accessed (A)
|
|
// 06 | Dirty (D)
|
|
// 07 | PAT (if PAT is supported, reserved otherwise)
|
|
// 08 | Global (G) (if CR4.PGE=1, ignored otherwise)
|
|
// 11-09 | (ignored)
|
|
// PA-12 | Physical address of the 4-KByte page
|
|
// 51-PA | Reserved (must be zero)
|
|
// 62-52 | ignored in long mode, reserved (must be 0) in legacy PAE mode
|
|
// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
|
|
// -----------------------------------------------------------
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
// Translate a linear address to a physical address in long mode
|
|
bx_phy_address BX_CPU_C::translate_linear_long_mode(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw)
|
|
{
|
|
bx_phy_address entry_addr[4];
|
|
bx_phy_address ppf = BX_CPU_THIS_PTR cr3 & BX_CR3_PAGING_MASK;
|
|
Bit64u entry[4];
|
|
bx_bool nx_fault = 0;
|
|
int leaf = BX_LEVEL_PTE;
|
|
combined_access = 0x06;
|
|
|
|
for (leaf = BX_LEVEL_PML4;; --leaf) {
|
|
entry_addr[leaf] = ppf + ((laddr >> (9 + 9*leaf)) & 0xff8);
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
|
|
entry_addr[leaf] = translate_guest_physical(entry_addr[leaf], laddr, 1, 1, BX_READ);
|
|
}
|
|
#endif
|
|
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, (BX_PTE_ACCESS + (leaf<<4)) | BX_READ, (Bit8u*)(&entry[leaf]));
|
|
|
|
Bit64u curr_entry = entry[leaf];
|
|
int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, PAGING_PAE_RESERVED_BITS, rw, &nx_fault);
|
|
if (fault >= 0)
|
|
page_fault(fault, laddr, user, rw);
|
|
|
|
combined_access &= curr_entry & 0x06; // U/S and R/W
|
|
ppf = curr_entry & BX_CONST64(0x000ffffffffff000);
|
|
|
|
if (leaf == BX_LEVEL_PTE) break;
|
|
|
|
if (curr_entry & 0x80) {
|
|
if (leaf > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging())) {
|
|
BX_DEBUG(("%s: PS bit set !", bx_paging_level[leaf]));
|
|
page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
if (leaf == BX_LEVEL_PDPE) {
|
|
if (curr_entry & PAGING_PAE_PDPTE1G_RESERVED_BITS) {
|
|
BX_DEBUG(("PAE PDPE1G: reserved bit is set: PDPE=%08x:%08x", GET32H(curr_entry), GET32L(curr_entry)));
|
|
page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = (bx_phy_address)((curr_entry & BX_CONST64(0x000fffffc0000000)) | (laddr & 0x3ffff000));
|
|
lpf_mask = 0x3fffffff;
|
|
break;
|
|
}
|
|
|
|
if (leaf == BX_LEVEL_PDE) {
|
|
if (curr_entry & PAGING_PAE_PDE2M_RESERVED_BITS) {
|
|
BX_DEBUG(("PAE PDE2M: reserved bit is set PDE=%08x:%08x", GET32H(curr_entry), GET32L(curr_entry)));
|
|
page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = (bx_phy_address)((curr_entry & BX_CONST64(0x000fffffffe00000)) | (laddr & 0x001ff000));
|
|
lpf_mask = 0x1fffff;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
bx_bool isWrite = (rw & 1); // write or r-m-w
|
|
|
|
unsigned priv_index = (BX_CPU_THIS_PTR cr0.get_WP() << 4) | // bit 4
|
|
(user<<3) | // bit 3
|
|
(combined_access | isWrite); // bit 2,1,0
|
|
|
|
if (!priv_check[priv_index] || nx_fault)
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_SMEP() && rw == BX_EXECUTE && !user) {
|
|
if (combined_access & 0x4) // User page
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE())
|
|
combined_access |= (entry[leaf] & 0x100); // G
|
|
|
|
// Update A bit if needed.
|
|
for (int level=BX_LEVEL_PML4; level > leaf; level--) {
|
|
if (!(entry[level] & 0x20)) {
|
|
entry[level] |= 0x20;
|
|
access_write_physical(entry_addr[level], 8, &entry[level]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[level], 8,
|
|
(BX_PTE_ACCESS + (level<<4)) | BX_WRITE, (Bit8u*)(&entry[level]));
|
|
}
|
|
}
|
|
|
|
// Update A/D bits if needed.
|
|
if (!(entry[leaf] & 0x20) || (isWrite && !(entry[leaf] & 0x40))) {
|
|
entry[leaf] |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8,
|
|
(BX_PTE_ACCESS + (leaf<<4)) | BX_WRITE, (Bit8u*)(&entry[leaf]));
|
|
}
|
|
|
|
return ppf;
|
|
}
|
|
|
|
#endif
|
|
|
|
// Format of Legacy PAE PDPTR entry (PDPTE)
|
|
// -----------------------------------------------------------
|
|
// 00 | Present (P)
|
|
// 02-01 | Reserved (must be zero)
|
|
// 03 | Page-Level Write-Through (PWT) (486+), 0=reserved otherwise
|
|
// 04 | Page-Level Cache-Disable (PCD) (486+), 0=reserved otherwise
|
|
// 08-05 | Reserved (must be zero)
|
|
// 11-09 | (ignored)
|
|
// PA-12 | Physical address of 4-KByte aligned page directory
|
|
// 63-PA | Reserved (must be zero)
|
|
// -----------------------------------------------------------
|
|
|
|
#define PAGING_PAE_PDPTE_RESERVED_BITS \
|
|
(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0xFFF00000000001E6))
|
|
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(bx_phy_address cr3_val)
|
|
{
|
|
cr3_val &= 0xffffffe0;
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
|
|
cr3_val = translate_guest_physical(cr3_val, 0, 0, 0, BX_READ);
|
|
}
|
|
#endif
|
|
|
|
Bit64u pdptr[4];
|
|
int n;
|
|
|
|
for (n=0; n<4; n++) {
|
|
// read and check PDPTE entries
|
|
bx_phy_address pdpe_entry_addr = (bx_phy_address) (cr3_val | (n << 3));
|
|
access_read_physical(pdpe_entry_addr, 8, &(pdptr[n]));
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pdpe_entry_addr, 8,
|
|
(BX_PDPTR0_ACCESS + (n<<4)) | BX_READ, (Bit8u*) &(pdptr[n]));
|
|
|
|
if (pdptr[n] & 0x1) {
|
|
if (pdptr[n] & PAGING_PAE_PDPTE_RESERVED_BITS) return 0;
|
|
}
|
|
}
|
|
|
|
// load new PDPTRs
|
|
for (n=0; n<4; n++)
|
|
BX_CPU_THIS_PTR PDPTR_CACHE.entry[n] = pdptr[n];
|
|
|
|
BX_CPU_THIS_PTR PDPTR_CACHE.valid = 1;
|
|
|
|
return 1; /* PDPTRs are fine */
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX >= 2
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(Bit64u *pdptr)
|
|
{
|
|
for (int n=0; n<4; n++) {
|
|
if (pdptr[n] & 0x1) {
|
|
if (pdptr[n] & PAGING_PAE_PDPTE_RESERVED_BITS) return 0;
|
|
}
|
|
}
|
|
|
|
return 1; /* PDPTRs are fine */
|
|
}
|
|
#endif
|
|
|
|
// Translate a linear address to a physical address in PAE paging mode
|
|
bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw)
|
|
{
|
|
bx_phy_address entry_addr[3], ppf;
|
|
Bit64u entry[3];
|
|
bx_bool nx_fault = 0;
|
|
int leaf = BX_LEVEL_PTE;
|
|
combined_access = 0x06;
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (long_mode()) {
|
|
return translate_linear_long_mode(laddr, lpf_mask, combined_access, user, rw);
|
|
}
|
|
#endif
|
|
|
|
if (! BX_CPU_THIS_PTR PDPTR_CACHE.valid) {
|
|
BX_PANIC(("PDPTR_CACHE not valid !"));
|
|
if (! CheckPDPTR(BX_CPU_THIS_PTR cr3)) {
|
|
BX_ERROR(("translate_linear_PAE(): PDPTR check failed !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
}
|
|
|
|
entry[BX_LEVEL_PDPE] = BX_CPU_THIS_PTR PDPTR_CACHE.entry[(laddr >> 30) & 3];
|
|
|
|
int fault = check_entry_PAE("PDPE", entry[BX_LEVEL_PDPE], PAGING_PAE_PDPTE_RESERVED_BITS, rw, &nx_fault);
|
|
if (fault >= 0)
|
|
page_fault(fault, laddr, user, rw);
|
|
|
|
entry_addr[BX_LEVEL_PDE] = (bx_phy_address)((entry[BX_LEVEL_PDPE] & BX_CONST64(0x000ffffffffff000))
|
|
| ((laddr & 0x3fe00000) >> 18));
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
|
|
entry_addr[BX_LEVEL_PDE] = translate_guest_physical(entry_addr[BX_LEVEL_PDE], laddr, 1, 1, BX_READ);
|
|
}
|
|
#endif
|
|
access_read_physical(entry_addr[BX_LEVEL_PDE], 8, &entry[BX_LEVEL_PDE]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 8, BX_PDE_ACCESS | BX_READ, (Bit8u*)(&entry[BX_LEVEL_PDE]));
|
|
|
|
fault = check_entry_PAE("PDE", entry[BX_LEVEL_PDE], PAGING_PAE_RESERVED_BITS, rw, &nx_fault);
|
|
if (fault >= 0)
|
|
page_fault(fault, laddr, user, rw);
|
|
|
|
combined_access &= entry[BX_LEVEL_PDE] & 0x06; // U/S and R/W
|
|
|
|
// Ignore CR4.PSE in PAE mode
|
|
if (entry[BX_LEVEL_PDE] & 0x80) {
|
|
if (entry[BX_LEVEL_PDE] & PAGING_PAE_PDE2M_RESERVED_BITS) {
|
|
BX_DEBUG(("PAE PDE2M: reserved bit is set PDE=%08x:%08x", GET32H(entry[BX_LEVEL_PDE]), GET32L(entry[BX_LEVEL_PDE])));
|
|
page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
ppf = (bx_phy_address)((entry[BX_LEVEL_PDE] & BX_CONST64(0x000fffffffe00000)) | (laddr & 0x001ff000));
|
|
lpf_mask = 0x1fffff;
|
|
leaf = BX_LEVEL_PDE;
|
|
}
|
|
else {
|
|
// 4k pages, Get page table entry.
|
|
entry_addr[BX_LEVEL_PTE] = (bx_phy_address)((entry[BX_LEVEL_PDE] & BX_CONST64(0x000ffffffffff000)) |
|
|
((laddr & 0x001ff000) >> 9));
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
|
|
entry_addr[BX_LEVEL_PTE] = translate_guest_physical(entry_addr[BX_LEVEL_PTE], laddr, 1, 1, BX_READ);
|
|
}
|
|
#endif
|
|
access_read_physical(entry_addr[BX_LEVEL_PTE], 8, &entry[BX_LEVEL_PTE]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PTE], 8, BX_PTE_ACCESS | BX_READ, (Bit8u*)(&entry[BX_LEVEL_PTE]));
|
|
|
|
fault = check_entry_PAE("PTE", entry[BX_LEVEL_PTE], PAGING_PAE_RESERVED_BITS, rw, &nx_fault);
|
|
if (fault >= 0)
|
|
page_fault(fault, laddr, user, rw);
|
|
|
|
combined_access &= entry[BX_LEVEL_PTE] & 0x06; // U/S and R/W
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = (bx_phy_address)(entry[leaf] & BX_CONST64(0x000ffffffffff000));
|
|
lpf_mask = 0xfff;
|
|
}
|
|
|
|
bx_bool isWrite = (rw & 1); // write or r-m-w
|
|
|
|
unsigned priv_index = (BX_CPU_THIS_PTR cr0.get_WP() << 4) | // bit 4
|
|
(user<<3) | // bit 3
|
|
(combined_access | isWrite); // bit 2,1,0
|
|
|
|
if (!priv_check[priv_index] || nx_fault)
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_SMEP() && rw == BX_EXECUTE && !user) {
|
|
if (combined_access & 0x4) // User page
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE())
|
|
combined_access |= (entry[leaf] & 0x100); // G
|
|
|
|
if (leaf == BX_LEVEL_PTE) {
|
|
// Update PDE A bit if needed.
|
|
if (!(entry[BX_LEVEL_PDE] & 0x20)) {
|
|
entry[BX_LEVEL_PDE] |= 0x20;
|
|
access_write_physical(entry_addr[BX_LEVEL_PDE], 8, &entry[BX_LEVEL_PDE]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 8,
|
|
(BX_PDE_ACCESS | BX_WRITE), (Bit8u*)(&entry[BX_LEVEL_PDE]));
|
|
}
|
|
}
|
|
|
|
// Update A/D bits if needed.
|
|
if (!(entry[leaf] & 0x20) || (isWrite && !(entry[leaf] & 0x40))) {
|
|
entry[leaf] |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8,
|
|
(BX_PTE_ACCESS + (leaf<<4)) | BX_WRITE, (Bit8u*)(&entry[leaf]));
|
|
}
|
|
|
|
return ppf;
|
|
}
|
|
|
|
#endif
|
|
|
|
// Format of a PDE that Maps a 4-MByte Page
|
|
// -----------------------------------------------------------
|
|
// 00 | Present (P)
|
|
// 01 | R/W
|
|
// 02 | U/S
|
|
// 03 | Page-Level Write-Through (PWT)
|
|
// 04 | Page-Level Cache-Disable (PCD)
|
|
// 05 | Accessed (A)
|
|
// 06 | Dirty (D)
|
|
// 07 | Page size, must be 1 to indicate 4-Mbyte page
|
|
// 08 | Global (G) (if CR4.PGE=1, ignored otherwise)
|
|
// 11-09 | (ignored)
|
|
// 12 | PAT (if PAT is supported, reserved otherwise)
|
|
// PA-13 | Bits PA-32 of physical address of the 4-MByte page
|
|
// 21-PA | Reserved (must be zero)
|
|
// 31-22 | Bits 31-22 of physical address of the 4-MByte page
|
|
// -----------------------------------------------------------
|
|
|
|
#define PAGING_PDE4M_RESERVED_BITS \
|
|
(((1 << (41-BX_PHY_ADDRESS_WIDTH))-1) << (13 + BX_PHY_ADDRESS_WIDTH - 32))
|
|
|
|
// Translate a linear address to a physical address
|
|
bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned user, unsigned rw)
|
|
{
|
|
Bit32u combined_access = 0x06;
|
|
Bit32u lpf_mask = 0xfff; // 4K pages
|
|
unsigned priv_index;
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (! long_mode()) laddr &= 0xffffffff;
|
|
#endif
|
|
|
|
// note - we assume physical memory < 4gig so for brevity & speed, we'll use
|
|
// 32 bit entries although cr3 is expanded to 64 bits.
|
|
bx_phy_address paddress, ppf, poffset = PAGE_OFFSET(laddr);
|
|
unsigned isWrite = rw & 1; // write or r-m-w
|
|
unsigned isExecute = (rw == BX_EXECUTE);
|
|
|
|
InstrTLB_Increment(tlbLookups);
|
|
InstrTLB_Stats();
|
|
|
|
bx_address lpf = LPFOf(laddr);
|
|
unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
|
|
|
|
// already looked up TLB for code access
|
|
if (TLB_LPFOf(tlbEntry->lpf) == lpf)
|
|
{
|
|
paddress = tlbEntry->ppf | poffset;
|
|
|
|
if (! (tlbEntry->accessBits & ((isExecute<<2) | (isWrite<<1) | user)))
|
|
return paddress;
|
|
|
|
// The current access does not have permission according to the info
|
|
// in our TLB cache entry. Re-walk the page tables, in case there is
|
|
// updated information in the memory image, and let the long path code
|
|
// generate an exception if one is warranted.
|
|
}
|
|
|
|
if(BX_CPU_THIS_PTR cr0.get_PG())
|
|
{
|
|
InstrTLB_Increment(tlbMisses);
|
|
|
|
BX_DEBUG(("page walk for address 0x" FMT_LIN_ADDRX, laddr));
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE()) {
|
|
ppf = translate_linear_PAE(laddr, lpf_mask, combined_access, user, rw);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
// CR4.PAE==0 (and EFER.LMA==0)
|
|
Bit32u pde, pte, cr3_masked = (Bit32u) BX_CPU_THIS_PTR cr3 & BX_CR3_PAGING_MASK;
|
|
|
|
bx_phy_address pde_addr = (bx_phy_address) (cr3_masked | ((laddr & 0xffc00000) >> 20));
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
|
|
pde_addr = translate_guest_physical(pde_addr, laddr, 1, 1, BX_READ);
|
|
}
|
|
#endif
|
|
access_read_physical(pde_addr, 4, &pde);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_PDE_ACCESS | BX_READ, (Bit8u*)(&pde));
|
|
|
|
if (!(pde & 0x1)) {
|
|
BX_DEBUG(("PDE: entry not present"));
|
|
page_fault(ERROR_NOT_PRESENT, laddr, user, rw);
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 5
|
|
if ((pde & 0x80) && BX_CPU_THIS_PTR cr4.get_PSE()) {
|
|
// 4M paging, only if CR4.PSE enabled, ignore PDE.PS otherwise
|
|
if (pde & PAGING_PDE4M_RESERVED_BITS) {
|
|
BX_DEBUG(("PSE PDE4M: reserved bit is set: PDE=0x%08x", pde));
|
|
page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
// Combined access is just access from the pde (no pte involved).
|
|
combined_access = pde & 0x06; // U/S and R/W
|
|
|
|
priv_index =
|
|
(BX_CPU_THIS_PTR cr0.get_WP() << 4) | // bit 4
|
|
(user<<3) | // bit 3
|
|
(combined_access | isWrite); // bit 2,1,0
|
|
|
|
if (!priv_check[priv_index])
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (BX_CPU_THIS_PTR cr4.get_SMEP() && isExecute && !user) {
|
|
if (combined_access & 0x4) // User page
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE())
|
|
combined_access |= pde & 0x100; // G
|
|
#endif
|
|
|
|
// Update PDE A/D bits if needed.
|
|
if (!(pde & 0x20) || (isWrite && !(pde & 0x40))) {
|
|
pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
access_write_physical(pde_addr, 4, &pde);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_PDE_ACCESS | BX_WRITE, (Bit8u*)(&pde));
|
|
}
|
|
|
|
// make up the physical frame number
|
|
ppf = (pde & 0xffc00000) | (laddr & 0x003ff000);
|
|
#if BX_PHY_ADDRESS_WIDTH > 32
|
|
ppf |= ((bx_phy_address)(pde & 0x003fe000)) << 19;
|
|
#endif
|
|
lpf_mask = 0x3fffff;
|
|
}
|
|
else // else normal 4K page...
|
|
#endif
|
|
{
|
|
// Get page table entry
|
|
bx_phy_address pte_addr = (bx_phy_address)((pde & 0xfffff000) | ((laddr & 0x003ff000) >> 10));
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
|
|
pte_addr = translate_guest_physical(pte_addr, laddr, 1, 1, BX_READ);
|
|
}
|
|
#endif
|
|
access_read_physical(pte_addr, 4, &pte);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pte_addr, 4, BX_PTE_ACCESS | BX_READ, (Bit8u*)(&pte));
|
|
|
|
if (!(pte & 0x1)) {
|
|
BX_DEBUG(("PTE: entry not present"));
|
|
page_fault(ERROR_NOT_PRESENT, laddr, user, rw);
|
|
}
|
|
|
|
// 386 and 486+ have different behaviour for combining
|
|
// privilege from PDE and PTE.
|
|
#if BX_CPU_LEVEL == 3
|
|
combined_access = (pde | pte) & 0x04; // U/S
|
|
combined_access |= (pde & pte) & 0x02; // R/W
|
|
#else // 486+
|
|
combined_access = (pde & pte) & 0x06; // U/S and R/W
|
|
#endif
|
|
|
|
priv_index =
|
|
#if BX_CPU_LEVEL >= 4
|
|
(BX_CPU_THIS_PTR cr0.get_WP() << 4) | // bit 4
|
|
#endif
|
|
(user<<3) | // bit 3
|
|
(combined_access | isWrite); // bit 2,1,0
|
|
|
|
if (!priv_check[priv_index])
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (BX_CPU_THIS_PTR cr4.get_SMEP() && isExecute && !user) {
|
|
if (combined_access & 0x4) // User page
|
|
page_fault(ERROR_PROTECTION, laddr, user, rw);
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE())
|
|
combined_access |= (pte & 0x100); // G
|
|
#endif
|
|
|
|
// Update PDE A bit if needed.
|
|
if (!(pde & 0x20)) {
|
|
pde |= 0x20;
|
|
access_write_physical(pde_addr, 4, &pde);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pde_addr, 4, BX_PDE_ACCESS | BX_WRITE, (Bit8u*)(&pde));
|
|
}
|
|
|
|
// Update PTE A/D bits if needed.
|
|
if (!(pte & 0x20) || (isWrite && !(pte & 0x40))) {
|
|
pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
|
|
access_write_physical(pte_addr, 4, &pte);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pte_addr, 4, BX_PTE_ACCESS | BX_WRITE, (Bit8u*)(&pte));
|
|
}
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = pte & 0xfffff000;
|
|
}
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 5
|
|
if (lpf_mask > 0xfff)
|
|
BX_CPU_THIS_PTR TLB.split_large = 1;
|
|
#endif
|
|
}
|
|
else {
|
|
// no paging
|
|
ppf = (bx_phy_address) lpf;
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
|
|
ppf = translate_guest_physical(ppf, laddr, 1, 0, rw);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// Calculate physical memory address and fill in TLB cache entry
|
|
paddress = A20ADDR(ppf | poffset);
|
|
|
|
// direct memory access is NOT allowed by default
|
|
tlbEntry->lpf = lpf | TLB_HostPtr;
|
|
tlbEntry->lpf_mask = lpf_mask;
|
|
tlbEntry->ppf = ppf;
|
|
tlbEntry->accessBits = 0;
|
|
|
|
if ((combined_access & 4) == 0) { // System
|
|
tlbEntry->accessBits |= TLB_SysOnly;
|
|
if (! isWrite)
|
|
tlbEntry->accessBits |= TLB_ReadOnly;
|
|
}
|
|
else {
|
|
// Current operation is a read or a page is read only
|
|
// Not efficient handling of system write to user read only page:
|
|
// hopefully it is very rare case, optimize later
|
|
if (! isWrite || (combined_access & 2) == 0) {
|
|
tlbEntry->accessBits |= TLB_ReadOnly;
|
|
}
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (combined_access & 0x100) // Global bit
|
|
tlbEntry->accessBits |= TLB_GlobalPage;
|
|
#endif
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
// EFER.NXE change won't flush TLB
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE() && rw != BX_EXECUTE)
|
|
tlbEntry->accessBits |= TLB_NoExecute;
|
|
#endif
|
|
|
|
// Attempt to get a host pointer to this physical page. Put that
|
|
// pointer in the TLB cache. Note if the request is vetoed, NULL
|
|
// will be returned, and it's OK to OR zero in anyways.
|
|
tlbEntry->hostPageAddr = BX_CPU_THIS_PTR getHostMemAddr(ppf, rw);
|
|
if (tlbEntry->hostPageAddr) {
|
|
// All access allowed also via direct pointer
|
|
#if BX_X86_DEBUGGER
|
|
if (! hwbreakpoint_check(laddr, BX_HWDebugMemW, BX_HWDebugMemRW))
|
|
#endif
|
|
tlbEntry->lpf = lpf; // allow direct access with HostPtr
|
|
}
|
|
|
|
return paddress;
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX >= 2
|
|
|
|
/* EPT access type */
|
|
#define BX_EPT_READ 0x01
|
|
#define BX_EPT_WRITE 0x02
|
|
#define BX_EPT_EXECUTE 0x04
|
|
|
|
/* EPT access mask */
|
|
#define BX_EPT_ENTRY_NOT_PRESENT 0x00
|
|
#define BX_EPT_ENTRY_READ_ONLY 0x01
|
|
#define BX_EPT_ENTRY_WRITE_ONLY 0x02
|
|
#define BX_EPT_ENTRY_READ_WRITE 0x03
|
|
#define BX_EPT_ENTRY_EXECUTE_ONLY 0x04
|
|
#define BX_EPT_ENTRY_READ_EXECUTE 0x05
|
|
#define BX_EPT_ENTRY_WRITE_EXECUTE 0x06
|
|
#define BX_EPT_ENTRY_READ_WRITE_EXECUTE 0x07
|
|
|
|
// Format of a EPT Entry
|
|
// -----------------------------------------------------------
|
|
// 00 | Read access
|
|
// 01 | Write access
|
|
// 02 | Execute Access
|
|
// 05-03 | EPT Memory type (for leaf entries, reserved otherwise)
|
|
// 06 | Ignore PAT memory type (for leaf entries, reserved otherwise)
|
|
// 07 | Page Size, must be 1 to indicate a Large Page
|
|
// 11-08 | (ignored)
|
|
// PA-12 | Physical address
|
|
// 51-PA | Reserved (must be zero)
|
|
// 63-52 | (ignored)
|
|
// -----------------------------------------------------------
|
|
|
|
#define PAGING_EPT_RESERVED_BITS (BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
|
|
|
|
bx_phy_address BX_CPU_C::translate_guest_physical(bx_phy_address guest_paddr, bx_address guest_laddr, bx_bool guest_laddr_valid, bx_bool is_page_walk, unsigned rw)
|
|
{
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
bx_phy_address entry_addr[4], ppf = 0, pbase = LPFOf(vm->eptptr);
|
|
Bit64u entry[4];
|
|
int leaf = BX_LEVEL_PTE;
|
|
Bit32u combined_access = 0x7, access_mask = 0;
|
|
|
|
BX_DEBUG(("EPT walk for guest paddr 0x" FMT_ADDRX, guest_paddr));
|
|
|
|
if (rw == BX_EXECUTE) access_mask |= BX_EPT_EXECUTE;
|
|
if (rw & 1) access_mask |= BX_EPT_WRITE; // write or r-m-w
|
|
if (rw == BX_READ) access_mask |= BX_EPT_READ;
|
|
|
|
Bit32u vmexit_reason = 0, vmexit_qualification = access_mask;
|
|
|
|
for (leaf = BX_LEVEL_PML4;; --leaf) {
|
|
entry_addr[leaf] = pbase + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
|
|
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8,
|
|
(BX_EPT_PTE_ACCESS + (leaf<<4)) | BX_READ, (Bit8u*)(&entry[leaf]));
|
|
|
|
Bit64u curr_entry = entry[leaf];
|
|
Bit32u curr_access_mask = curr_entry & 0x7;
|
|
|
|
combined_access &= curr_access_mask;
|
|
|
|
if (curr_access_mask == BX_EPT_ENTRY_NOT_PRESENT) {
|
|
BX_DEBUG(("EPT %s: not present", bx_paging_level[leaf]));
|
|
vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
|
|
break;
|
|
}
|
|
|
|
if (curr_access_mask == BX_EPT_ENTRY_WRITE_ONLY || curr_access_mask == BX_EPT_ENTRY_WRITE_EXECUTE) {
|
|
BX_DEBUG(("EPT %s: EPT misconfiguration mask=%d",
|
|
bx_paging_level[leaf], curr_access_mask));
|
|
vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
|
|
break;
|
|
}
|
|
|
|
extern bx_bool isMemTypeValidMTRR(unsigned memtype);
|
|
if (! isMemTypeValidMTRR((curr_entry >> 3) & 7)) {
|
|
BX_DEBUG(("EPT %s: EPT misconfiguration memtype=%d", bx_paging_level[leaf], (curr_entry >> 3) & 7));
|
|
vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
|
|
break;
|
|
}
|
|
|
|
if (curr_entry & PAGING_EPT_RESERVED_BITS) {
|
|
BX_DEBUG(("EPT %s: reserved bit is set %08x:%08x",
|
|
bx_paging_level[leaf], GET32H(curr_entry), GET32L(curr_entry)));
|
|
vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
|
|
break;
|
|
}
|
|
|
|
pbase = curr_entry & BX_CONST64(0x000ffffffffff000);
|
|
|
|
if (leaf == BX_LEVEL_PTE) {
|
|
// Make up the physical page frame address.
|
|
ppf = (bx_phy_address)(curr_entry & BX_CONST64(0x000ffffffffff000));
|
|
break;
|
|
}
|
|
|
|
if (curr_entry & 0x80) {
|
|
if (leaf > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging())) {
|
|
BX_DEBUG(("EPT %s: PS bit set !", bx_paging_level[leaf]));
|
|
vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
|
|
break;
|
|
}
|
|
|
|
if (leaf == BX_LEVEL_PDPE) {
|
|
if (curr_entry & PAGING_PAE_PDPTE1G_RESERVED_BITS) {
|
|
BX_DEBUG(("EPT PDPE1G: reserved bit is set: PDPE=%08x:%08x", GET32H(curr_entry), GET32L(curr_entry)));
|
|
vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
|
|
break;
|
|
}
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = (bx_phy_address)((curr_entry & BX_CONST64(0x000fffffc0000000)) | (guest_paddr & 0x3ffff000));
|
|
break;
|
|
}
|
|
|
|
if (leaf == BX_LEVEL_PDE) {
|
|
if (curr_entry & PAGING_PAE_PDE2M_RESERVED_BITS) {
|
|
BX_DEBUG(("EPT PDE2M: reserved bit is set PDE=%08x:%08x", GET32H(curr_entry), GET32L(curr_entry)));
|
|
vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
|
|
break;
|
|
}
|
|
|
|
// Make up the physical page frame address.
|
|
ppf = (bx_phy_address)((curr_entry & BX_CONST64(0x000fffffffe00000)) | (guest_paddr & 0x001ff000));
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if ((access_mask & combined_access) != access_mask) {
|
|
vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
|
|
}
|
|
|
|
if (vmexit_reason) {
|
|
BX_ERROR(("VMEXIT: EPT %s for guest paddr 0x" FMT_ADDRX " laddr " FMT_ADDRX,
|
|
(vmexit_reason == VMX_VMEXIT_EPT_VIOLATION) ? "violation" : "misconfig", guest_paddr, guest_laddr));
|
|
VMwrite64(VMCS_64BIT_GUEST_PHYSICAL_ADDR, guest_paddr);
|
|
if (guest_laddr_valid) {
|
|
VMwrite_natural(VMCS_GUEST_LINEAR_ADDR, guest_laddr);
|
|
vmexit_qualification |= 0x80;
|
|
if (is_page_walk) vmexit_qualification |= 0x100;
|
|
}
|
|
VMexit(0, vmexit_reason, vmexit_qualification | (combined_access << 3));
|
|
}
|
|
|
|
Bit32u page_offset = PAGE_OFFSET(guest_paddr);
|
|
return ppf | page_offset;
|
|
}
|
|
|
|
#endif
|
|
|
|
#if BX_DEBUGGER || BX_DISASM || BX_INSTRUMENTATION || BX_GDBSTUB
|
|
|
|
#if BX_DEBUGGER
|
|
|
|
void dbg_print_paging_pte(int level, Bit64u entry)
|
|
{
|
|
dbg_printf("%4s: 0x%08x%08x", bx_paging_level[level], GET32H(entry), GET32L(entry));
|
|
|
|
if (level == BX_LEVEL_PTE) {
|
|
dbg_printf(" %s %s %s",
|
|
(entry & 0x0100) ? "G" : "g",
|
|
(entry & 0x0080) ? "PAT" : "pat",
|
|
(entry & 0x0040) ? "D" : "d");
|
|
}
|
|
else {
|
|
if (entry & 0x80) {
|
|
dbg_printf(" PS %s %s %s",
|
|
(entry & 0x0100) ? "G" : "g",
|
|
(entry & 0x1000) ? "PAT" : "pat",
|
|
(entry & 0x0040) ? "D" : "d");
|
|
}
|
|
else {
|
|
dbg_printf(" ps ");
|
|
}
|
|
}
|
|
|
|
dbg_printf(" %s %s %s %s %s %s\n",
|
|
(entry & 0x20) ? "A" : "a",
|
|
(entry & 0x10) ? "PCD" : "pcd",
|
|
(entry & 0x08) ? "PWT" : "pwt",
|
|
(entry & 0x04) ? "U" : "S",
|
|
(entry & 0x02) ? "W" : "R",
|
|
(entry & 0x01) ? "P" : "p");
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX >= 2
|
|
void dbg_print_ept_paging_pte(int level, Bit64u entry)
|
|
{
|
|
dbg_printf("EPT %4s: 0x%08x%08x", bx_paging_level[level], GET32H(entry), GET32L(entry));
|
|
|
|
if (level != BX_LEVEL_PTE && (entry & 0x80))
|
|
dbg_printf(" PS");
|
|
else
|
|
dbg_printf(" ");
|
|
|
|
dbg_printf(" %s %s %s\n",
|
|
(entry & 0x04) ? "E" : "e",
|
|
(entry & 0x02) ? "W" : "w",
|
|
(entry & 0x01) ? "R" : "r");
|
|
}
|
|
#endif
|
|
|
|
#endif // BX_DEBUGGER
|
|
|
|
#if BX_SUPPORT_VMX >= 2
|
|
bx_bool BX_CPU_C::dbg_translate_guest_physical(bx_phy_address guest_paddr, bx_phy_address *phy, bx_bool verbose)
|
|
{
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
bx_phy_address pt_address = LPFOf(vm->eptptr);
|
|
Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
|
|
|
|
for (int level = 3; level >= 0; --level) {
|
|
Bit64u pte;
|
|
pt_address += ((guest_paddr >> (9 + 9*level)) & 0xff8);
|
|
offset_mask >>= 9;
|
|
BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, pt_address, 8, &pte);
|
|
#if BX_DEBUGGER
|
|
if (verbose)
|
|
dbg_print_ept_paging_pte(level, pte);
|
|
#endif
|
|
switch(pte & 7) {
|
|
case BX_EPT_ENTRY_NOT_PRESENT:
|
|
case BX_EPT_ENTRY_WRITE_ONLY:
|
|
case BX_EPT_ENTRY_WRITE_EXECUTE:
|
|
return 0;
|
|
}
|
|
if (pte & BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
|
|
return 0;
|
|
|
|
pt_address = bx_phy_address(pte & BX_CONST64(0x000ffffffffff000));
|
|
|
|
if (level == BX_LEVEL_PTE) break;
|
|
|
|
if (pte & 0x80) {
|
|
if (level > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging()))
|
|
return 0;
|
|
|
|
pt_address &= BX_CONST64(0x000fffffffffe000);
|
|
if (pt_address & offset_mask) return 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
*phy = pt_address + (bx_phy_address)(guest_paddr & offset_mask);
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
bx_bool BX_CPU_C::dbg_xlate_linear2phy(bx_address laddr, bx_phy_address *phy, bx_bool verbose)
|
|
{
|
|
bx_phy_address paddress;
|
|
|
|
if (! BX_CPU_THIS_PTR cr0.get_PG()) {
|
|
paddress = (bx_phy_address) laddr;
|
|
}
|
|
else {
|
|
bx_phy_address pt_address = BX_CPU_THIS_PTR cr3 & BX_CR3_PAGING_MASK;
|
|
|
|
// see if page is in the TLB first
|
|
if (! verbose) {
|
|
bx_address lpf = LPFOf(laddr);
|
|
unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
|
|
|
|
if (TLB_LPFOf(tlbEntry->lpf) == lpf) {
|
|
paddress = tlbEntry->ppf | PAGE_OFFSET(laddr);
|
|
*phy = paddress;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (BX_CPU_THIS_PTR cr4.get_PAE()) {
|
|
Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
|
|
|
|
int level = 3;
|
|
if (! long_mode()) {
|
|
if (! BX_CPU_THIS_PTR PDPTR_CACHE.valid)
|
|
goto page_fault;
|
|
pt_address = BX_CPU_THIS_PTR PDPTR_CACHE.entry[(laddr >> 30) & 3] & BX_CONST64(0x000ffffffffff000);
|
|
offset_mask >>= 18;
|
|
level = 1;
|
|
}
|
|
|
|
for (; level >= 0; --level) {
|
|
Bit64u pte;
|
|
pt_address += ((laddr >> (9 + 9*level)) & 0xff8);
|
|
offset_mask >>= 9;
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
|
|
if (! dbg_translate_guest_physical(pt_address, &pt_address, verbose))
|
|
goto page_fault;
|
|
}
|
|
}
|
|
#endif
|
|
BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, pt_address, 8, &pte);
|
|
#if BX_DEBUGGER
|
|
if (verbose)
|
|
dbg_print_paging_pte(level, pte);
|
|
#endif
|
|
if(!(pte & 1))
|
|
goto page_fault;
|
|
if (pte & BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
|
|
goto page_fault;
|
|
pt_address = bx_phy_address(pte & BX_CONST64(0x000ffffffffff000));
|
|
if (level == BX_LEVEL_PTE) break;
|
|
if (pte & 0x80) {
|
|
// 2M page
|
|
if (level == BX_LEVEL_PDE) {
|
|
pt_address &= BX_CONST64(0x000fffffffffe000);
|
|
if (pt_address & offset_mask)
|
|
goto page_fault;
|
|
break;
|
|
}
|
|
// 1G page
|
|
if (bx_cpuid_support_1g_paging() && level == BX_LEVEL_PDPE && long_mode()) {
|
|
pt_address &= BX_CONST64(0x000fffffffffe000);
|
|
if (pt_address & offset_mask)
|
|
goto page_fault;
|
|
break;
|
|
}
|
|
goto page_fault;
|
|
}
|
|
}
|
|
paddress = pt_address + (bx_phy_address)(laddr & offset_mask);
|
|
}
|
|
else // not PAE
|
|
#endif
|
|
{
|
|
Bit32u offset_mask = 0xfff;
|
|
for (int level = 1; level >= 0; --level) {
|
|
Bit32u pte;
|
|
pt_address += ((laddr >> (10 + 10*level)) & 0xffc);
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
|
|
if (! dbg_translate_guest_physical(pt_address, &pt_address, verbose))
|
|
goto page_fault;
|
|
}
|
|
}
|
|
#endif
|
|
BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, pt_address, 4, &pte);
|
|
#if BX_DEBUGGER
|
|
if (verbose)
|
|
dbg_print_paging_pte(level, pte);
|
|
#endif
|
|
if (!(pte & 1))
|
|
goto page_fault;
|
|
pt_address = pte & 0xfffff000;
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (level == BX_LEVEL_PDE && (pte & 0x80) != 0 && BX_CPU_THIS_PTR cr4.get_PSE()) {
|
|
offset_mask = 0x3fffff;
|
|
pt_address = pte & 0xffc00000;
|
|
#if BX_PHY_ADDRESS_WIDTH > 32
|
|
pt_address += ((bx_phy_address)(pte & 0x003fe000)) << 19;
|
|
#endif
|
|
break;
|
|
}
|
|
#endif
|
|
}
|
|
paddress = pt_address + (bx_phy_address)(laddr & offset_mask);
|
|
}
|
|
}
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
|
|
if (! dbg_translate_guest_physical(paddress, &paddress, verbose))
|
|
goto page_fault;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
*phy = A20ADDR(paddress);
|
|
return 1;
|
|
|
|
page_fault:
|
|
*phy = 0;
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void BX_CPU_C::access_write_linear(bx_address laddr, unsigned len, unsigned curr_pl, void *data)
|
|
{
|
|
#if BX_X86_DEBUGGER
|
|
hwbreakpoint_match(laddr, len, BX_WRITE);
|
|
#endif
|
|
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
|
|
/* check for reference across multiple pages */
|
|
if ((pageOffset + len) <= 4096) {
|
|
// Access within single page.
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(laddr, (curr_pl==3), BX_WRITE);
|
|
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, BX_CPU_THIS_PTR address_xlation.paddress1, len, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
len, curr_pl, BX_WRITE, (Bit8u*) data);
|
|
|
|
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
|
|
}
|
|
else {
|
|
// access across 2 pages
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(laddr, (curr_pl == 3), BX_WRITE);
|
|
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
|
BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
|
bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
|
|
#if BX_SUPPORT_X86_64
|
|
if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
|
|
#endif
|
|
BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(laddr2, (curr_pl == 3), BX_WRITE);
|
|
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
|
|
BX_WRITE, (Bit8u*) data);
|
|
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, data);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, curr_pl,
|
|
BX_WRITE, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
#else // BX_BIG_ENDIAN
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
|
|
BX_WRITE, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
|
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, curr_pl,
|
|
BX_WRITE, (Bit8u*) data);
|
|
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, data);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_pl, unsigned xlate_rw, void *data)
|
|
{
|
|
BX_ASSERT(xlate_rw == BX_READ || xlate_rw == BX_RW);
|
|
|
|
#if BX_X86_DEBUGGER
|
|
hwbreakpoint_match(laddr, len, xlate_rw);
|
|
#endif
|
|
|
|
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
|
|
|
/* check for reference across multiple pages */
|
|
if ((pageOffset + len) <= 4096) {
|
|
// Access within single page.
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(laddr, (curr_pl == 3), xlate_rw);
|
|
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, len, xlate_rw);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, len, curr_pl,
|
|
BX_READ, (Bit8u*) data);
|
|
}
|
|
else {
|
|
// access across 2 pages
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(laddr, (curr_pl == 3), xlate_rw);
|
|
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
|
BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
|
bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
|
|
#if BX_SUPPORT_X86_64
|
|
if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
|
|
#endif
|
|
BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(laddr2, (curr_pl == 3), xlate_rw);
|
|
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, data);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
|
|
BX_READ, (Bit8u*) data);
|
|
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, curr_pl,
|
|
BX_READ, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
#else // BX_BIG_ENDIAN
|
|
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
|
|
BX_READ, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
|
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, data);
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2, curr_pl,
|
|
BX_READ, (Bit8u*) data);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::access_write_physical(bx_phy_address paddr, unsigned len, void *data)
|
|
{
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (is_virtual_apic_page(paddr)) {
|
|
VMX_Virtual_Apic_Write(paddr, len, data);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_APIC
|
|
if (BX_CPU_THIS_PTR lapic.is_selected(paddr)) {
|
|
BX_CPU_THIS_PTR lapic.write(paddr, data, len);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS, paddr, len, data);
|
|
}
|
|
|
|
void BX_CPU_C::access_read_physical(bx_phy_address paddr, unsigned len, void *data)
|
|
{
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (is_virtual_apic_page(paddr)) {
|
|
VMX_Virtual_Apic_Read(paddr, len, data);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_APIC
|
|
if (BX_CPU_THIS_PTR lapic.is_selected(paddr)) {
|
|
BX_CPU_THIS_PTR lapic.read(paddr, data, len);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, paddr, len, data);
|
|
}
|
|
|
|
bx_hostpageaddr_t BX_CPU_C::getHostMemAddr(bx_phy_address ppf, unsigned rw)
|
|
{
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (is_virtual_apic_page(ppf))
|
|
return 0; // Do not allow direct access to virtual apic page
|
|
#endif
|
|
|
|
#if BX_SUPPORT_APIC
|
|
if (BX_CPU_THIS_PTR lapic.is_selected(ppf))
|
|
return 0; // Vetoed! APIC address space
|
|
#endif
|
|
|
|
return (bx_hostpageaddr_t) BX_MEM(0)->getHostMemAddr(BX_CPU_THIS, ppf, rw);
|
|
}
|
|
|
|
#if BX_LARGE_RAMFILE
|
|
bx_bool BX_CPU_C::check_addr_in_tlb_buffers(const Bit8u *addr, const Bit8u *end)
|
|
{
|
|
for (unsigned tlb_entry_num=0; tlb_entry_num < BX_TLB_SIZE; tlb_entry_num++) {
|
|
if (((BX_CPU_THIS_PTR TLB.entry[tlb_entry_num].hostPageAddr)>=(const bx_hostpageaddr_t)addr) &&
|
|
((BX_CPU_THIS_PTR TLB.entry[tlb_entry_num].hostPageAddr)<(const bx_hostpageaddr_t)end))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
#endif
|