402b2c01c9
Only missed AVX-512 opcodes are: 512.66.0F38.W0 2C VSCALEFPS 512.66.0F38.W1 2C VSCALEFPD NDS.LIG.66.0F38.W0 2D VSCALESS NDS.LIG.66.0F38.W1 2D VSCALESD
111 lines
3.4 KiB
C++
111 lines
3.4 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2014 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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// AVX-512 conflict detection instructions
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#if BX_SUPPORT_EVEX
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#include "simd_int.h"
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#include "scalar_arith.h"
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCONFLICTD_MASK_VdqWdqR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
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unsigned len = i->getVL();
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for (unsigned n=0; n < DWORD_ELEMENTS(len); n++) {
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op.vmm32u(n) = simd_pconflictd(&op, n);
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}
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if (i->opmask()) {
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avx512_write_regd_masked(i, &op, len, BX_READ_16BIT_OPMASK(i->opmask()));
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}
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else {
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BX_WRITE_AVX_REGZ(i->dst(), op, len);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCONFLICTQ_MASK_VdqWdqR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
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unsigned len = i->getVL();
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for (unsigned n=0; n < QWORD_ELEMENTS(len); n++) {
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op.vmm64u(n) = simd_pconflictq(&op, n);
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}
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if (i->opmask()) {
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avx512_write_regq_masked(i, &op, len, BX_READ_8BIT_OPMASK(i->opmask()));
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}
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else {
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BX_WRITE_AVX_REGZ(i->dst(), op, len);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTMB2Q_VdqKEbR(bxInstruction_c *i)
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{
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simd_pbroadcastq(&BX_AVX_REG(i->dst()), (Bit64u) BX_READ_8BIT_OPMASK(i->src()), QWORD_ELEMENTS(i->getVL()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTMW2D_VdqKEwR(bxInstruction_c *i)
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{
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simd_pbroadcastd(&BX_AVX_REG(i->dst()), (Bit32u) BX_READ_16BIT_OPMASK(i->src()), DWORD_ELEMENTS(i->getVL()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPLZCNTD_MASK_VdqWdqR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
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unsigned len = i->getVL();
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for (unsigned n=0; n < DWORD_ELEMENTS(len); n++)
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op.vmm32u(n) = lzcntd(op.vmm32u(n));
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avx512_write_regd_masked(i, &op, len, BX_READ_16BIT_OPMASK(i->opmask()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPLZCNTQ_MASK_VdqWdqR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
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unsigned len = i->getVL();
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for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
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op.vmm64u(n) = lzcntq(op.vmm64u(n));
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avx512_write_regq_masked(i, &op, len, BX_READ_8BIT_OPMASK(i->opmask()));
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BX_NEXT_INSTR(i);
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}
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#endif
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