119 lines
4.2 KiB
Plaintext
119 lines
4.2 KiB
Plaintext
From zwane@linux.realnet.co.sz Thu Mar 28 11:59:40 2002
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Date: Thu, 21 Mar 2002 08:21:29 +0200 (SAST)
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From: Zwane Mwaikambo <zwane@linux.realnet.co.sz>
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To: Bochs Devel <bochs-developers@lists.sourceforge.net>
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Subject: [Bochs-developers] [PATCH] bochs_smp_pge_pic_poll
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This patch is to get us a bit closer in booting linux 2.4 SMP
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(tested with 4-way) with all the bells and whistles. This was tested with
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2.5.7-pre1, the PGE part of it we just play along and try follow
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the global page semantics (avoid flushing global pages in specific
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places) and is required for PPro+ kernels in linux. The PIC poll code
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allows polling mode, in this mode we don't have to do anything and let
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the host OS do everything.
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Zwane
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diff -ur bochs-1.3-zm1/cpu/cpu.h /build/source/bochs-1.3/cpu/cpu.h
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--- bochs-1.3-zm1/cpu/cpu.h Wed Mar 20 06:59:07 2002
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+++ /build/source/bochs-1.3/cpu/cpu.h Wed Mar 20 22:26:31 2002
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@@ -871,6 +871,7 @@
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struct {
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bx_TLB_entry entry[BX_TLB_SIZE];
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} TLB;
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+ Boolean skip_global_pages;
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#endif
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struct {
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diff -ur bochs-1.3-zm1/cpu/paging.cc /build/source/bochs-1.3/cpu/paging.cc
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--- bochs-1.3-zm1/cpu/paging.cc Wed Oct 3 15:10:37 2001
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+++ /build/source/bochs-1.3/cpu/paging.cc Wed Mar 20 23:09:51 2002
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@@ -358,6 +358,7 @@
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#if BX_USE_TLB
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unsigned i;
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unsigned wp, us_combined, rw_combined, us_current, rw_current;
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+ skip_global_pages = false;
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for (i=0; i<BX_TLB_SIZE; i++) {
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BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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@@ -403,9 +404,20 @@
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BX_CPU_C::TLB_flush(void)
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{
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#if BX_USE_TLB
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+ Bit32u pte;
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for (unsigned i=0; i<BX_TLB_SIZE; i++) {
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- BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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+ /* don't invalidate if Global (8) bit set */
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+ if (skip_global_pages) {
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+ BX_CPU_THIS_PTR mem->read_physical(this,
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+ BX_CPU_THIS_PTR TLB.entry[i].pte_addr,
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+ 4, &pte);
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+ /* check if the global bit is set for this pte */
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+ if (pte & (1<<8))
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+ continue;
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}
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+
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+ BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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+ }
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#endif // #if BX_USE_TLB
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invalidate_prefetch_q();
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diff -ur bochs-1.3-zm1/cpu/proc_ctrl.cc /build/source/bochs-1.3/cpu/proc_ctrl.cc
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--- bochs-1.3-zm1/cpu/proc_ctrl.cc Mon Mar 11 08:07:35 2002
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+++ /build/source/bochs-1.3/cpu/proc_ctrl.cc Wed Mar 20 22:42:19 2002
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@@ -504,17 +504,14 @@
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#else
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// Protected mode: #GP(0) if attempt to write a 1 to
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// any reserved bit of CR4
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+ if ((val_32 >> 10) & 0x7ff)
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+ exception(BX_GP_EXCEPTION, 0, 0);
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- BX_INFO(("MOV_CdRd: ignoring write to CR4 of 0x%08x",
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- val_32));
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- if (val_32) {
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- BX_INFO(("MOV_CdRd: (CR4) write of 0x%08x not supported!",
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- val_32));
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- }
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- // Only allow writes of 0 to CR4 for now.
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- // Writes to bits in CR4 should not be 1s as CPUID
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- // returns not-supported for all of these features.
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- BX_CPU_THIS_PTR cr4 = 0;
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+ BX_CPU_THIS_PTR cr4 = val_32;
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+ // this also has the side effect of flushing the tlb
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+ // including pages marked as global.
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+ TLB_flush();
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+ skip_global_pages = (val_32 & (1<<4)) ? true: false;
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#endif
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break;
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default:
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@@ -1032,6 +1029,7 @@
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model = 1; // Pentium Pro
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stepping = 3; // ???
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features |= (1<<4); // implement TSC
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+ features |= (1<<13); // support PGE
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# if BX_SUPPORT_APIC
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features |= (1<<9); // APIC on chip
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# endif
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diff -ur bochs-1.3-zm1/iodev/pic.cc /build/source/bochs-1.3/iodev/pic.cc
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--- bochs-1.3-zm1/iodev/pic.cc Tue Nov 27 20:15:39 2001
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+++ /build/source/bochs-1.3/iodev/pic.cc Thu Mar 21 07:11:02 2002
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@@ -243,7 +243,10 @@
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poll = (value & 0x04) >> 2;
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read_op = (value & 0x03);
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if (poll)
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- BX_PANIC(("pic:master:OCW3: poll bit set"));
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+ /* if we're in polling mode, the os executive has to do all the work,
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+ * linux 2.4 does this for the timer interrupt on systems with an IOAPIC
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+ */
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+ return;
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if (read_op == 0x02) /* read IRR */
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BX_PIC_THIS s.master_pic.read_reg_select = 0;
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else if (read_op == 0x03) /* read ISR */
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_______________________________________________
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bochs-developers mailing list
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bochs-developers@lists.sourceforge.net
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https://lists.sourceforge.net/lists/listinfo/bochs-developers
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