ac4e5bb6cf
- don't allow MMX on cpu level < 5.
- require FPU support on cpu level >= 55
- don't allow MMX support without FPU support (moved this check from
cpu/i387.h to config.h)
158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
#ifndef BX_I387_RELATED_EXTENSIONS_H
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#define BX_I387_RELATED_EXTENSIONS_H
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/* Get data sizes from config.h generated from simulator's
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* configure script
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*/
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#include "config.h"
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typedef Bit8u u8; /* for FPU only */
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typedef Bit8s s8;
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typedef Bit16u u16;
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typedef Bit16s s16;
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typedef Bit32u u32;
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typedef Bit32s s32;
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typedef Bit64u u64;
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typedef Bit64s s64;
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//
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// Minimal i387 structure, pruned from the linux headers. Only
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// the fields which were necessary are included.
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//
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struct BxFpuRegisters {
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s32 cwd;
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s32 swd;
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s32 twd;
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s32 fip;
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s32 fcs;
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s32 foo;
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s32 fos;
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u32 fill0; /* to make sure the following aligns on an 8byte boundary */
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u64 st_space[16]; /* 8*16 bytes per FP-reg (aligned) = 128 bytes */
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unsigned char ftop;
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unsigned char no_update;
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unsigned char rm;
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unsigned char alimit;
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};
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#if BX_SUPPORT_MMX
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typedef union {
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Bit8u u8;
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Bit8s s8;
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} MMX_BYTE;
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typedef union {
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Bit16u u16;
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Bit16s s16;
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struct {
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#ifdef BX_BIG_ENDIAN
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MMX_BYTE hi;
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MMX_BYTE lo;
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#else
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MMX_BYTE lo;
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MMX_BYTE hi;
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#endif
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} bytes;
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} MMX_WORD;
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typedef union {
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Bit32u u32;
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Bit32s s32;
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struct {
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#ifdef BX_BIG_ENDIAN
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MMX_WORD hi;
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MMX_WORD lo;
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#else
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MMX_WORD lo;
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MMX_WORD hi;
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#endif
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} words;
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} MMX_DWORD;
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typedef union {
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Bit64u u64;
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Bit64s s64;
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struct {
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#ifdef BX_BIG_ENDIAN
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MMX_DWORD hi;
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MMX_DWORD lo;
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#else
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MMX_DWORD lo;
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MMX_DWORD hi;
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#endif
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} dwords;
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} MMX_QWORD, BxPackedMmxRegister;
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#define MMXSB0(reg) (reg.dwords.lo.words.lo.bytes.lo.s8)
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#define MMXSB1(reg) (reg.dwords.lo.words.lo.bytes.hi.s8)
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#define MMXSB2(reg) (reg.dwords.lo.words.hi.bytes.lo.s8)
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#define MMXSB3(reg) (reg.dwords.lo.words.hi.bytes.hi.s8)
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#define MMXSB4(reg) (reg.dwords.hi.words.lo.bytes.lo.s8)
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#define MMXSB5(reg) (reg.dwords.hi.words.lo.bytes.hi.s8)
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#define MMXSB6(reg) (reg.dwords.hi.words.hi.bytes.lo.s8)
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#define MMXSB7(reg) (reg.dwords.hi.words.hi.bytes.hi.s8)
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#define MMXUB0(reg) (reg.dwords.lo.words.lo.bytes.lo.u8)
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#define MMXUB1(reg) (reg.dwords.lo.words.lo.bytes.hi.u8)
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#define MMXUB2(reg) (reg.dwords.lo.words.hi.bytes.lo.u8)
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#define MMXUB3(reg) (reg.dwords.lo.words.hi.bytes.hi.u8)
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#define MMXUB4(reg) (reg.dwords.hi.words.lo.bytes.lo.u8)
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#define MMXUB5(reg) (reg.dwords.hi.words.lo.bytes.hi.u8)
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#define MMXUB6(reg) (reg.dwords.hi.words.hi.bytes.lo.u8)
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#define MMXUB7(reg) (reg.dwords.hi.words.hi.bytes.hi.u8)
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#define MMXSW0(reg) (reg.dwords.lo.words.lo.s16)
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#define MMXSW1(reg) (reg.dwords.lo.words.hi.s16)
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#define MMXSW2(reg) (reg.dwords.hi.words.lo.s16)
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#define MMXSW3(reg) (reg.dwords.hi.words.hi.s16)
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#define MMXUW0(reg) (reg.dwords.lo.words.lo.u16)
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#define MMXUW1(reg) (reg.dwords.lo.words.hi.u16)
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#define MMXUW2(reg) (reg.dwords.hi.words.lo.u16)
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#define MMXUW3(reg) (reg.dwords.hi.words.hi.u16)
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#define MMXSD0(reg) (reg.dwords.lo.s32)
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#define MMXSD1(reg) (reg.dwords.hi.s32)
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#define MMXUD0(reg) (reg.dwords.lo.u32)
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#define MMXUD1(reg) (reg.dwords.hi.u32)
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#define MMXSQ(reg) (reg.s64)
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#define MMXUQ(reg) (reg.u64)
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typedef struct mmx_physical_reg_t
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{
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BxPackedMmxRegister packed_mmx_register;
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Bit16u exp; /* 4 bytes: exponent of fp register,
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set to 0xFFFF by all mmx commands */
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Bit32u aligment; /* 4 bytes: aligment */
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} BxMmxRegister;
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/* to be compatible with fpu register file */
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struct BxMmxRegisters
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{
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Bit32u cwd; /* fpu control word */
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Bit32u swd; /* fpu status word */
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Bit32u twd; /* fpu tag word */
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Bit32u fip;
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Bit32u fcs;
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Bit32u foo;
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Bit32u fos;
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Bit32u alignment;
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BxMmxRegister mmx[8];
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unsigned char tos; /* top-of-stack */
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unsigned char no_update;
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unsigned char rm;
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unsigned char alimit;
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};
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#endif /* BX_SUPPORT_MMX */
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typedef union FpuMmxRegisters
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{
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struct BxFpuRegisters soft;
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#if BX_SUPPORT_MMX
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struct BxMmxRegisters mmx;
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#endif
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} i387_t;
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#endif
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