8952c144bd
- Fixed PCI BAR initialization (now using memset()). - Fixed reset failure (set all PAM memory types to ROM). - Added stub for the AGP aperture (register BAR #0, handle APSIZE and read GART entry in read/write handlers). - Added some more PCI register defaults and write masks. - Fixed a warning in the ES1370 code. - Voodoo Banshee: set up PCI subsystem ID depending on bus and model. - Volatile BIOS write support must also be present in ISA BIOS memory.
475 lines
14 KiB
C++
475 lines
14 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2018 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// PCI-to-ISA bridge
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// i430FX - PIIX
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// i440FX - PIIX3
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// i440BX - PIIX4
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI
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#include "pci.h"
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#include "pci2isa.h"
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#define LOG_THIS thePci2IsaBridge->
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bx_piix3_c *thePci2IsaBridge = NULL;
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int CDECL libpci2isa_LTX_plugin_init(plugin_t *plugin, plugintype_t type)
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{
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if (type == PLUGTYPE_CORE) {
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thePci2IsaBridge = new bx_piix3_c();
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bx_devices.pluginPci2IsaBridge = thePci2IsaBridge;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePci2IsaBridge, BX_PLUGIN_PCI2ISA);
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return 0; // Success
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} else {
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return -1;
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}
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}
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void CDECL libpci2isa_LTX_plugin_fini(void)
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{
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delete thePci2IsaBridge;
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}
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bx_piix3_c::bx_piix3_c()
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{
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put("pci2isa", "P2ISA");
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}
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bx_piix3_c::~bx_piix3_c()
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{
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SIM->get_bochs_root()->remove("pci2isa");
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BX_DEBUG(("Exit"));
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}
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void bx_piix3_c::init(void)
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{
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unsigned i, j;
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// called once when bochs initializes
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BX_P2I_THIS s.chipset = SIM->get_param_enum(BXPN_PCI_CHIPSET)->get();
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if (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I440BX) {
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BX_P2I_THIS s.devfunc = BX_PCI_DEVICE(7, 0);
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} else {
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BX_P2I_THIS s.devfunc = BX_PCI_DEVICE(1, 0);
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}
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DEV_register_pci_handlers(this, &BX_P2I_THIS s.devfunc, BX_PLUGIN_PCI2ISA,
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"PIIX3 PCI-to-ISA bridge");
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DEV_register_iowrite_handler(this, write_handler, 0x00B2, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_iowrite_handler(this, write_handler, 0x00B3, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_iowrite_handler(this, write_handler, 0x04D0, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_iowrite_handler(this, write_handler, 0x04D1, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_iowrite_handler(this, write_handler, 0x0CF9, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_ioread_handler(this, read_handler, 0x00B2, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_ioread_handler(this, read_handler, 0x00B3, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_ioread_handler(this, read_handler, 0x04D0, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_ioread_handler(this, read_handler, 0x04D1, "PIIX3 PCI-to-ISA bridge", 1);
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DEV_register_ioread_handler(this, read_handler, 0x0CF9, "PIIX3 PCI-to-ISA bridge", 1);
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for (i=0; i<16; i++)
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BX_P2I_THIS s.irq_registry[i] = 0x0;
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for (i=0; i<4; i++) {
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for (j=0; j<16; j++) {
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BX_P2I_THIS s.irq_level[i][j] = 0x0;
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}
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}
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// initialize readonly registers
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if (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I430FX) {
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init_pci_conf(0x8086, 0x122e, 0x01, 0x060100, 0x80, 0);
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} else if (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I440BX) {
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init_pci_conf(0x8086, 0x7110, 0x00, 0x060100, 0x80, 0);
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} else {
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init_pci_conf(0x8086, 0x7000, 0x00, 0x060100, 0x80, 0);
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}
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BX_P2I_THIS pci_conf[0x04] = 0x07;
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// irq routing registers
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BX_P2I_THIS pci_conf[0x60] = 0x80;
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BX_P2I_THIS pci_conf[0x61] = 0x80;
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BX_P2I_THIS pci_conf[0x62] = 0x80;
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BX_P2I_THIS pci_conf[0x63] = 0x80;
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#if BX_DEBUGGER
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// register device for the 'info device' command (calls debug_dump())
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bx_dbg_register_debug_info("pci2isa", this);
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#endif
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}
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void bx_piix3_c::reset(unsigned type)
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{
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BX_P2I_THIS pci_conf[0x05] = 0x00;
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BX_P2I_THIS pci_conf[0x06] = 0x00;
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BX_P2I_THIS pci_conf[0x07] = 0x02;
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BX_P2I_THIS pci_conf[0x4c] = 0x4d;
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BX_P2I_THIS pci_conf[0x4e] = 0x03;
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BX_P2I_THIS pci_conf[0x4f] = 0x00;
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BX_P2I_THIS pci_conf[0x69] = 0x02;
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BX_P2I_THIS pci_conf[0x70] = 0x80;
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BX_P2I_THIS pci_conf[0x76] = 0x0c;
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BX_P2I_THIS pci_conf[0x77] = 0x0c;
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BX_P2I_THIS pci_conf[0x78] = 0x02;
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BX_P2I_THIS pci_conf[0x79] = 0x00;
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BX_P2I_THIS pci_conf[0x80] = 0x00;
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BX_P2I_THIS pci_conf[0x82] = 0x00;
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BX_P2I_THIS pci_conf[0xa0] = 0x08;
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BX_P2I_THIS pci_conf[0xa2] = 0x00;
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BX_P2I_THIS pci_conf[0xa3] = 0x00;
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BX_P2I_THIS pci_conf[0xa4] = 0x00;
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BX_P2I_THIS pci_conf[0xa5] = 0x00;
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BX_P2I_THIS pci_conf[0xa6] = 0x00;
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BX_P2I_THIS pci_conf[0xa7] = 0x00;
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BX_P2I_THIS pci_conf[0xa8] = 0x0f;
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BX_P2I_THIS pci_conf[0xaa] = 0x00;
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BX_P2I_THIS pci_conf[0xab] = 0x00;
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BX_P2I_THIS pci_conf[0xac] = 0x00;
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BX_P2I_THIS pci_conf[0xae] = 0x00;
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for (unsigned i = 0; i < 4; i++) {
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pci_set_irq(BX_P2I_THIS s.devfunc, i+1, 0);
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pci_unregister_irq(i, 0x80);
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}
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BX_P2I_THIS s.elcr1 = 0x00;
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BX_P2I_THIS s.elcr2 = 0x00;
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BX_P2I_THIS s.pci_reset = 0x00;
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BX_P2I_THIS s.apms = 0x00;
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BX_P2I_THIS s.apmc = 0x00;
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}
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void bx_piix3_c::register_state(void)
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{
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unsigned i, j;
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char name[6];
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci2isa", "PCI-to-ISA Bridge State");
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register_pci_state(list);
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BXRS_HEX_PARAM_FIELD(list, elcr1, BX_P2I_THIS s.elcr1);
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BXRS_HEX_PARAM_FIELD(list, elcr2, BX_P2I_THIS s.elcr2);
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BXRS_HEX_PARAM_FIELD(list, apmc, BX_P2I_THIS s.apmc);
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BXRS_HEX_PARAM_FIELD(list, apms, BX_P2I_THIS s.apms);
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BXRS_HEX_PARAM_FIELD(list, pci_reset, BX_P2I_THIS s.pci_reset);
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new bx_shadow_data_c(list, "irq_registry", BX_P2I_THIS s.irq_registry, 16, 1);
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bx_list_c *irql = new bx_list_c(list, "irq_level");
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for (i=0; i<4; i++) {
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for (j=0; j<16; j++) {
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sprintf(name, "%u_%u", i, j);
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new bx_shadow_num_c(irql, name, &BX_P2I_THIS s.irq_level[i][j]);
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}
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}
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}
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void bx_piix3_c::after_restore_state(void)
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{
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for (unsigned i=0; i<16; i++) {
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if (BX_P2I_THIS s.irq_registry[i]) {
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DEV_register_irq(i, "PIIX3 IRQ routing");
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}
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}
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}
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void bx_piix3_c::pci_register_irq(unsigned pirq, Bit8u irq)
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{
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if ((irq < 16) && (((1 << irq) & 0xdef8) > 0)) {
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if (BX_P2I_THIS pci_conf[0x60 + pirq] < 16) {
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pci_unregister_irq(pirq, irq);
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}
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BX_P2I_THIS pci_conf[0x60 + pirq] = irq;
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if (!BX_P2I_THIS s.irq_registry[irq]) {
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DEV_register_irq(irq, "PIIX3 IRQ routing");
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}
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BX_P2I_THIS s.irq_registry[irq] |= (1 << pirq);
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}
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}
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void bx_piix3_c::pci_unregister_irq(unsigned pirq, Bit8u irq)
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{
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Bit8u oldirq = BX_P2I_THIS pci_conf[0x60 + pirq];
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if (oldirq < 16) {
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BX_P2I_THIS s.irq_registry[oldirq] &= ~(1 << pirq);
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if (!BX_P2I_THIS s.irq_registry[oldirq]) {
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BX_P2I_THIS pci_set_irq(BX_P2I_THIS s.devfunc, pirq+1, 0);
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DEV_unregister_irq(oldirq, "PIIX3 IRQ routing");
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}
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BX_P2I_THIS pci_conf[0x60 + pirq] = irq;
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}
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}
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void bx_piix3_c::pci_set_irq(Bit8u devfunc, unsigned line, bx_bool level)
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{
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Bit8u offset = (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I440BX) ? 8 : 2;
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Bit8u pirq = ((devfunc >> 3) + line - offset) & 0x03;
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#if BX_SUPPORT_APIC
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// forward this function call to the ioapic too
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if (DEV_ioapic_present()) {
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DEV_ioapic_set_irq_level(pirq + 16, level);
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}
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#endif
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Bit8u irq = BX_P2I_THIS pci_conf[0x60 + pirq];
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if ((irq < 16) && (((1 << irq) & 0xdef8) > 0)) {
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if (level == 1) {
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if (!BX_P2I_THIS s.irq_level[0][irq] && !BX_P2I_THIS s.irq_level[1][irq] &&
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!BX_P2I_THIS s.irq_level[2][irq] && !BX_P2I_THIS s.irq_level[3][irq]) {
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DEV_pic_raise_irq(irq);
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BX_DEBUG(("PIRQ%c -> IRQ %d = 1", pirq+65, irq));
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}
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BX_P2I_THIS s.irq_level[pirq][irq] |= (1 << (devfunc >> 3));
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} else {
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BX_P2I_THIS s.irq_level[pirq][irq] &= ~(1 << (devfunc >> 3));
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if (!BX_P2I_THIS s.irq_level[0][irq] && !BX_P2I_THIS s.irq_level[1][irq] &&
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!BX_P2I_THIS s.irq_level[2][irq] && !BX_P2I_THIS s.irq_level[3][irq]) {
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DEV_pic_lower_irq(irq);
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BX_DEBUG(("PIRQ%c -> IRQ %d = 0", pirq+65, irq));
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}
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}
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}
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u bx_piix3_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_P2I_SMF
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bx_piix3_c *class_ptr = (bx_piix3_c *) this_ptr;
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return class_ptr->read(address, io_len);
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}
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Bit32u bx_piix3_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_P2I_SMF
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switch (address) {
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case 0x00b2:
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return(BX_P2I_THIS s.apmc);
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case 0x00b3:
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return(BX_P2I_THIS s.apms);
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case 0x04d0:
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return(BX_P2I_THIS s.elcr1);
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case 0x04d1:
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return(BX_P2I_THIS s.elcr2);
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case 0x0cf9:
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return(BX_P2I_THIS s.pci_reset);
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}
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return(0xffffffff);
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void bx_piix3_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_P2I_SMF
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bx_piix3_c *class_ptr = (bx_piix3_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void bx_piix3_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_P2I_SMF
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switch (address) {
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case 0x00b2:
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if (PLUG_device_present(BX_PLUGIN_ACPI)) {
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DEV_acpi_generate_smi((Bit8u)value);
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} else {
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BX_ERROR(("write 0x%02x: APM command register not supported without ACPI", value));
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}
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BX_P2I_THIS s.apmc = value & 0xff;
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break;
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case 0x00b3:
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BX_P2I_THIS s.apms = value & 0xff;
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break;
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case 0x04d0:
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value &= 0xf8;
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if (value != BX_P2I_THIS s.elcr1) {
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BX_P2I_THIS s.elcr1 = value;
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BX_INFO(("write: ELCR1 = 0x%02x", BX_P2I_THIS s.elcr1));
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DEV_pic_set_mode(1, BX_P2I_THIS s.elcr1); // master PIC
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}
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break;
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case 0x04d1:
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value &= 0xde;
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if (value != BX_P2I_THIS s.elcr2) {
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BX_P2I_THIS s.elcr2 = value;
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BX_INFO(("write: ELCR2 = 0x%02x", BX_P2I_THIS s.elcr2));
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DEV_pic_set_mode(0, BX_P2I_THIS s.elcr2); // slave PIC
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}
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break;
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case 0x0cf9:
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BX_INFO(("write: CPU reset register = 0x%02x", value));
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BX_P2I_THIS s.pci_reset = value & 0x02;
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if (value & 0x04) {
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if (BX_P2I_THIS s.pci_reset) {
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bx_pc_system.Reset(BX_RESET_HARDWARE);
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} else {
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bx_pc_system.Reset(BX_RESET_SOFTWARE);
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}
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}
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break;
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}
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}
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// pci configuration space write callback handler
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void bx_piix3_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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{
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Bit8u value8, oldval;
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if ((address >= 0x10) && (address < 0x34))
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return;
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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oldval = BX_P2I_THIS pci_conf[address+i];
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switch (address+i) {
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case 0x04:
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BX_P2I_THIS pci_conf[address+i] = (value8 & 0x08) | 0x07;
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break;
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case 0x05:
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if (BX_P2I_THIS s.chipset != BX_PCI_CHIPSET_I430FX) {
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BX_P2I_THIS pci_conf[address+i] = (value8 & 0x01);
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}
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break;
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case 0x06:
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break;
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case 0x07:
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if (BX_P2I_THIS s.chipset == BX_PCI_CHIPSET_I430FX) {
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value8 &= 0x38;
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} else {
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value8 &= 0x78;
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}
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BX_P2I_THIS pci_conf[address+i] = (oldval & ~value8) | 0x02;
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break;
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case 0x4e:
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if ((value8 & 0x04) != (oldval & 0x04)) {
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BX_DEBUG(("Set BIOS write support to %d", (value8 & 0x04) != 0));
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DEV_mem_set_bios_write((value8 & 0x04) != 0);
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}
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BX_P2I_THIS pci_conf[address+i] = value8;
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break;
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case 0x4f:
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if (BX_P2I_THIS s.chipset != BX_PCI_CHIPSET_I430FX) {
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BX_P2I_THIS pci_conf[address+i] = (value8 & 0x01);
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#if BX_SUPPORT_APIC
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if (DEV_ioapic_present()) {
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DEV_ioapic_set_enabled(value8 & 0x01, (BX_P2I_THIS pci_conf[0x80] & 0x3f) << 10);
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}
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#endif
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}
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break;
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case 0x60:
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|
case 0x61:
|
|
case 0x62:
|
|
case 0x63:
|
|
value8 &= 0x8f;
|
|
if (value8 != oldval) {
|
|
if (value8 >= 0x80) {
|
|
pci_unregister_irq((address+i) & 0x03, value8);
|
|
} else {
|
|
pci_register_irq((address+i) & 0x03, value8);
|
|
}
|
|
BX_INFO(("PCI IRQ routing: PIRQ%c# set to 0x%02x", address+i-31,
|
|
value8));
|
|
}
|
|
break;
|
|
case 0x6a:
|
|
if (BX_P2I_THIS s.chipset != BX_PCI_CHIPSET_I430FX) {
|
|
// TODO: bit #4: enable / disable USB function at boot time
|
|
BX_P2I_THIS pci_conf[address+i] = (value8 & 0xd7);
|
|
}
|
|
break;
|
|
case 0x80:
|
|
if (BX_P2I_THIS s.chipset != BX_PCI_CHIPSET_I430FX) {
|
|
BX_P2I_THIS pci_conf[address+i] = (value8 & 0x7f);
|
|
#if BX_SUPPORT_APIC
|
|
if (DEV_ioapic_present()) {
|
|
DEV_ioapic_set_enabled(BX_P2I_THIS pci_conf[0x4f] & 0x01, (value8 & 0x3f) << 10);
|
|
}
|
|
#endif
|
|
}
|
|
break;
|
|
default:
|
|
BX_P2I_THIS pci_conf[address+i] = value8;
|
|
BX_DEBUG(("PIIX3 PCI-to-ISA write register 0x%02x value 0x%02x", address+i,
|
|
value8));
|
|
}
|
|
}
|
|
}
|
|
|
|
#if BX_DEBUGGER
|
|
void bx_piix3_c::debug_dump(int argc, char **argv)
|
|
{
|
|
int arg, i, j, r;
|
|
|
|
dbg_printf("PIIX3 ISA bridge\n\n");
|
|
dbg_printf("ELCR1 = 0x%02x\n", BX_P2I_THIS s.elcr1);
|
|
dbg_printf("ELCR2 = 0x%02x\n", BX_P2I_THIS s.elcr2);
|
|
if (argc == 0) {
|
|
for (i = 0; i < 4; i++) {
|
|
dbg_printf("PIRQ%c# = 0x%02x", i + 65, BX_P2I_THIS pci_conf[0x60 + i]);
|
|
Bit8u irq = BX_P2I_THIS pci_conf[0x60 + i];
|
|
if (irq < 16) {
|
|
dbg_printf(" (level=%d)\n", BX_P2I_THIS s.irq_level[i][irq] > 0);
|
|
} else {
|
|
dbg_printf("\n");
|
|
}
|
|
}
|
|
dbg_printf("\nSupported options:\n");
|
|
dbg_printf("info device 'pci2isa' 'dump=full' - show PCI config space\n");
|
|
} else {
|
|
for (arg = 0; arg < argc; arg++) {
|
|
if (!strcmp(argv[arg], "dump=full")) {
|
|
dbg_printf("\nPCI config space\n\n");
|
|
r = 0;
|
|
for (i=0; i<16; i++) {
|
|
dbg_printf("%04x ", r);
|
|
for (j=0; j<16; j++) {
|
|
dbg_printf(" %02x", BX_P2I_THIS pci_conf[r++]);
|
|
}
|
|
dbg_printf("\n");
|
|
}
|
|
} else {
|
|
dbg_printf("\nUnknown option: '%s'\n", argv[arg]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#endif /* BX_SUPPORT_PCI */
|