7f570b0150
PNI could be enabled by setting BX_SUPPORT_PNI in config.h After the feature will be fully validation I'll also add configure option. The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions. Enjoy ! ;)
628 lines
14 KiB
C++
628 lines
14 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer32.cc,v 1.28 2003-08-29 21:20:52 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::RETnear32_Iw(bxInstruction_c *i)
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{
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BailBigRSP("RETnear32_Iw");
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Bit16u imm16;
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Bit32u temp_ESP;
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Bit32u return_EIP;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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temp_ESP = ESP;
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else
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temp_ESP = SP;
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imm16 = i->Iw();
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if (protected_mode()) {
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if ( !can_pop(4) ) {
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BX_PANIC(("retnear_iw: can't pop EIP"));
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/* ??? #SS(0) -or #GP(0) */
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}
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
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4, CPL==3, BX_READ, &return_EIP);
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if (protected_mode() &&
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(return_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) ) {
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BX_DEBUG(("retnear_iw: EIP > limit"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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/* Pentium book says imm16 is number of words ??? */
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if ( !can_pop(4 + imm16) ) {
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BX_PANIC(("retnear_iw: can't release bytes from stack"));
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/* #GP(0) -or #SS(0) ??? */
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}
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EIP = return_EIP;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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ESP += 4 + imm16; /* ??? should it be 2*imm16 ? */
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else
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SP += 4 + imm16;
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}
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else {
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pop_32(&return_EIP);
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EIP = return_EIP;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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ESP += imm16; /* ??? should it be 2*imm16 ? */
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else
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SP += imm16;
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}
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
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}
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void
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BX_CPU_C::RETnear32(bxInstruction_c *i)
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{
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BailBigRSP("RETnear32");
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Bit32u temp_ESP;
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Bit32u return_EIP;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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temp_ESP = ESP;
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else
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temp_ESP = SP;
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if (protected_mode()) {
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if ( !can_pop(4) ) {
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BX_PANIC(("retnear: can't pop EIP"));
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/* ??? #SS(0) -or #GP(0) */
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}
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
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4, CPL==3, BX_READ, &return_EIP);
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if ( return_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("retnear: EIP > limit"));
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//exception(BX_GP_EXCEPTION, 0, 0);
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}
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EIP = return_EIP;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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ESP += 4;
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else
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SP += 4;
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}
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else {
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pop_32(&return_EIP);
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EIP = return_EIP;
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}
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
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}
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void
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BX_CPU_C::RETfar32_Iw(bxInstruction_c *i)
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{
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BailBigRSP("RETfar32_Iw");
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Bit32u eip, ecs_raw;
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Bit16s imm16;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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/* ??? is imm16, number of bytes/words depending on operandsize ? */
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imm16 = i->Iw();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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BX_CPU_THIS_PTR return_protected(i, imm16);
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goto done;
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}
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#endif
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pop_32(&eip);
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pop_32(&ecs_raw);
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EIP = eip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) ecs_raw);
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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ESP += imm16;
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else
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SP += imm16;
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::RETfar32(bxInstruction_c *i)
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{
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BailBigRSP("RETfar32");
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Bit32u eip, ecs_raw;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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#if BX_CPU_LEVEL >= 2
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR return_protected(i, 0);
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goto done;
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}
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#endif
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pop_32(&eip);
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pop_32(&ecs_raw); /* 32bit pop, MSW discarded */
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EIP = eip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) ecs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::CALL_Ad(bxInstruction_c *i)
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{
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BailBigRSP("CALL_Ad");
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Bit32u new_EIP;
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Bit32s disp32;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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disp32 = i->Id();
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new_EIP = EIP + disp32;
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if ( protected_mode() ) {
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if ( new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("call_av: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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/* push 32 bit EA of next instruction */
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push_32(EIP);
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EIP = new_EIP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void
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BX_CPU_C::CALL32_Ap(bxInstruction_c *i)
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{
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BailBigRSP("CALL32_Ap");
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Bit16u cs_raw;
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Bit32u disp32;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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disp32 = i->Id();
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cs_raw = i->Iw2();
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if (protected_mode()) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, disp32);
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goto done;
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}
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_32(EIP);
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EIP = disp32;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::CALL_Ed(bxInstruction_c *i)
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{
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BailBigRSP("CALL_Ed");
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Bit32u temp_ESP;
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Bit32u op1_32;
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//invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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temp_ESP = ESP;
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else
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temp_ESP = SP;
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (protected_mode()) {
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if (op1_32 >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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push_32(EIP);
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EIP = op1_32;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void
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BX_CPU_C::CALL32_Ep(bxInstruction_c *i)
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{
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BailBigRSP("CALL32_Ep");
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Bit16u cs_raw;
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Bit32u op1_32;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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BX_PANIC(("CALL_Ep: op1 is a register"));
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}
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_32);
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goto done;
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}
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_32(EIP);
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EIP = op1_32;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void
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BX_CPU_C::JMP_Jd(bxInstruction_c *i)
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{
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BailBigRSP("JMP_Jd");
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Bit32u new_EIP;
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//invalidate_prefetch_q();
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new_EIP = EIP + (Bit32s) i->Id();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jmp_jv: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
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}
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void
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BX_CPU_C::JCC_Jd(bxInstruction_c *i)
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{
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bx_bool condition;
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switch (i->b1() & 0x0f) {
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case 0x00: /* JO */ condition = get_OF(); break;
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case 0x01: /* JNO */ condition = !get_OF(); break;
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case 0x02: /* JB */ condition = get_CF(); break;
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case 0x03: /* JNB */ condition = !get_CF(); break;
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case 0x04: /* JZ */ condition = get_ZF(); break;
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case 0x05: /* JNZ */ condition = !get_ZF(); break;
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case 0x06: /* JBE */ condition = get_CF() || get_ZF(); break;
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case 0x07: /* JNBE */ condition = !get_CF() && !get_ZF(); break;
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case 0x08: /* JS */ condition = get_SF(); break;
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case 0x09: /* JNS */ condition = !get_SF(); break;
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case 0x0A: /* JP */ condition = get_PF(); break;
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case 0x0B: /* JNP */ condition = !get_PF(); break;
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case 0x0C: /* JL */ condition = getB_SF() != getB_OF(); break;
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case 0x0D: /* JNL */ condition = getB_SF() == getB_OF(); break;
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case 0x0E: /* JLE */ condition = get_ZF() || (getB_SF() != getB_OF());
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break;
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case 0x0F: /* JNLE */ condition = (getB_SF() == getB_OF()) &&
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!get_ZF();
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break;
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default:
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condition = 0; // For compiler...all targets should set condition.
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break;
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}
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if (condition) {
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BailBigRSP("JCC_Jd");
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Bit32u new_EIP;
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new_EIP = EIP + (Bit32s) i->Id();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled )
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{
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BX_PANIC(("jo_routine: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void
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BX_CPU_C::JZ_Jd(bxInstruction_c *i)
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{
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BailBigRSP("JZ_Jd");
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if (get_ZF()) {
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Bit32u new_EIP;
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new_EIP = EIP + (Bit32s) i->Id();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jo_routine: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void
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BX_CPU_C::JNZ_Jd(bxInstruction_c *i)
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{
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BailBigRSP("JNZ_Jd");
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if (!get_ZF()) {
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Bit32u new_EIP;
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new_EIP = EIP + (Bit32s) i->Id();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( new_EIP >
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_PANIC(("jo_routine: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#endif
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EIP = new_EIP;
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void
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BX_CPU_C::JMP_Ap(bxInstruction_c *i)
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{
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BailBigRSP("JMP_Ap");
|
|
Bit32u disp32;
|
|
Bit16u cs_raw;
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
if (i->os32L()) {
|
|
disp32 = i->Id();
|
|
}
|
|
else {
|
|
disp32 = i->Iw();
|
|
}
|
|
cs_raw = i->Iw2();
|
|
|
|
#if BX_CPU_LEVEL >= 2
|
|
if (protected_mode()) {
|
|
BX_CPU_THIS_PTR jump_protected(i, cs_raw, disp32);
|
|
goto done;
|
|
}
|
|
#endif
|
|
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
|
|
EIP = disp32;
|
|
|
|
done:
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
BX_CPU_C::JMP_Ed(bxInstruction_c *i)
|
|
{
|
|
BailBigRSP("JMP_Ed");
|
|
Bit32u new_EIP;
|
|
Bit32u op1_32;
|
|
|
|
//invalidate_prefetch_q();
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
}
|
|
|
|
new_EIP = op1_32;
|
|
|
|
#if BX_CPU_LEVEL >= 2
|
|
if (protected_mode()) {
|
|
if (new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
|
|
BX_PANIC(("jmp_ev: IP out of CS limits!"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
EIP = new_EIP;
|
|
|
|
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
|
|
}
|
|
|
|
/* Far indirect jump */
|
|
|
|
void
|
|
BX_CPU_C::JMP32_Ep(bxInstruction_c *i)
|
|
{
|
|
BailBigRSP("JMP32_Ep");
|
|
Bit16u cs_raw;
|
|
Bit32u op1_32;
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
/* far indirect must specify a memory address */
|
|
BX_PANIC(("JMP_Ep(): op1 is a register"));
|
|
}
|
|
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
|
|
|
|
if ( protected_mode() ) {
|
|
BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_32);
|
|
goto done;
|
|
}
|
|
|
|
EIP = op1_32;
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
|
|
|
|
done:
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::IRET32(bxInstruction_c *i)
|
|
{
|
|
BailBigRSP("IRET32");
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR show_flag |= Flag_iret;
|
|
BX_CPU_THIS_PTR show_eip = EIP;
|
|
#endif
|
|
|
|
if (v8086_mode()) {
|
|
// IOPL check in stack_return_from_v86()
|
|
stack_return_from_v86(i);
|
|
goto done;
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 2
|
|
if (BX_CPU_THIS_PTR cr0.pe) {
|
|
iret_protected(i);
|
|
goto done;
|
|
}
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 5
|
|
/*this feature discribed in pentium docs*/
|
|
if (iret32_real(i))
|
|
goto done;
|
|
#endif
|
|
|
|
BX_ERROR(("IRET32 may not be implemented right."));
|
|
BX_PANIC(("Please report that you have found a test case for BX_CPU_C::IRET32."));
|
|
|
|
done:
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
}
|