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Bochs/bochs/cpu
History
Stanislav Shwartsman 1765a06d01 move debug.h from bochs.h and include it only where required
2021-01-31 15:22:58 +00:00
..
avx
regen Makefile include dependencies for CPU and internal debugger
2021-01-30 20:17:15 +00:00
cpudb
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
decoder
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
fpu
regen Makefile include dependencies for CPU and internal debugger
2021-01-30 20:17:15 +00:00
3dnow.cc
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access2.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
access.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
access.h
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aes.cc
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apic.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
apic.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
arith8.cc
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arith16.cc
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arith32.cc
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arith64.cc
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bcd.cc
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bit16.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit32.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit64.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit.cc
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bmi32.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bmi64.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
call_far.cc
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cet.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
cpu.cc
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
cpu.h
move debug.h from bochs.h and include it only where required
2021-01-31 15:22:58 +00:00
cpuid.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
cpuid.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
cpustats.h
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crc32.cc
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crregs.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
crregs.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
ctrl_xfer16.cc
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ctrl_xfer32.cc
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ctrl_xfer64.cc
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ctrl_xfer_pro.cc
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data_xfer8.cc
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data_xfer16.cc
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data_xfer32.cc
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data_xfer64.cc
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debugstuff.cc
fixed compilation without bochs debugger
2021-01-30 20:31:03 +00:00
descriptor.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
event.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
exception.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
faststring.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
flag_ctrl_pro.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
flag_ctrl.cc
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fpu_emu.cc
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generic_cpuid.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
generic_cpuid.h
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gf2.cc
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i387.h
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icache.cc
fix compilation with SMP enabled
2021-01-31 14:03:28 +00:00
icache.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
init.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
io.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
iret.cc
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jmp_far.cc
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lazy_flags.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
load.cc
Fixed buffer overflow in LOAD_Wdq method when MXCSR.MM=1 -> thanks new gcc10 warning
2020-10-03 09:37:06 +00:00
logical8.cc
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logical16.cc
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logical32.cc
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logical64.cc
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Makefile.in
regen Makefile include dependencies for CPU and internal debugger
2021-01-30 20:17:15 +00:00
mmx.cc
fixed behavior of MMX PSRAW/PSRAD instructions when shift count is zero - still has to invalidate x87 tags for dest register
2020-12-15 20:05:54 +00:00
msr.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
msr.h
Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
2020-05-29 12:35:30 +00:00
mult8.cc
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mult16.cc
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mult32.cc
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mult64.cc
extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
2020-05-19 16:01:23 +00:00
mwait.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
paging.cc
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
proc_ctrl.cc
remove gui.h from bochs.h and include it only where required
2021-01-30 18:47:25 +00:00
protect_ctrl.cc
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rdrand.cc
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ret_far.cc
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scalar_arith.h
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segment_ctrl_pro.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
segment_ctrl.cc
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sha.cc
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shift8.cc
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shift16.cc
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shift32.cc
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shift64.cc
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simd_compare.h
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simd_int.h
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simd_pfp.h
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smm.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
smm.h
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soft_int.cc
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sse_move.cc
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sse_pfp.cc
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sse_rcp.cc
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sse_string.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
sse.cc
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stack16.cc
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stack32.cc
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stack64.cc
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stack.cc
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stack.h
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string.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
svm.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
svm.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
tasking.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
tlb.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
todo
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vapic.cc
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
vm8086.cc
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vmcs.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
vmexit.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
vmfunc.cc
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vmx.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
vmx.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
wide_int.cc
extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
2020-05-19 16:01:23 +00:00
wide_int.h
extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
2020-05-19 16:01:23 +00:00
xmm.h
implemented AVX encoded VNNI instructions published in recent SDM - not tested yet
2020-10-03 09:23:28 +00:00
xsave.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00