318 lines
14 KiB
C
318 lines
14 KiB
C
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2010-2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CPU_MODEL_SPECIFIC
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#define BX_CPU_MODEL_SPECIFIC
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struct cpuid_function_t {
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Bit32u eax;
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Bit32u ebx;
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Bit32u ecx;
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Bit32u edx;
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};
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// cpuid ISA (duplicated in disasm.h)
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#define BX_CPU_X87 (1 << 0) /* FPU (X87) instruction */
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#define BX_CPU_486 (1 << 1) /* 486 new instruction */
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#define BX_CPU_PENTIUM (1 << 2) /* Pentium new instruction */
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#define BX_CPU_P6 (1 << 3) /* P6 new instruction */
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#define BX_CPU_MMX (1 << 4) /* MMX instruction */
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#define BX_CPU_3DNOW (1 << 5) /* 3DNow! instruction */
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#define BX_CPU_FXSAVE_FXRSTOR (1 << 6) /* FXSAVE/FXRSTOR instruction */
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#define BX_CPU_SYSENTER_SYSEXIT (1 << 7) /* SYSENTER/SYSEXIT instruction */
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#define BX_CPU_CLFLUSH (1 << 8) /* CLFLUSH instruction */
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#define BX_CPU_SSE (1 << 9) /* SSE instruction */
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#define BX_CPU_SSE2 (1 << 10) /* SSE2 instruction */
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#define BX_CPU_SSE3 (1 << 11) /* SSE3 instruction */
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#define BX_CPU_SSSE3 (1 << 12) /* SSSE3 instruction */
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#define BX_CPU_SSE4_1 (1 << 13) /* SSE4_1 instruction */
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#define BX_CPU_SSE4_2 (1 << 14) /* SSE4_2 instruction */
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#define BX_CPU_MONITOR_MWAIT (1 << 15) /* MONITOR/MWAIT instruction */
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#define BX_CPU_VMX (1 << 16) /* VMX instruction */
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#define BX_CPU_SMX (1 << 17) /* SMX instruction */
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#define BX_CPU_SVM (1 << 18) /* SVM instruction */
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#define BX_CPU_XSAVE (1 << 19) /* XSAVE/XRSTOR extensions instruction */
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#define BX_CPU_XSAVEOPT (1 << 20) /* XSAVEOPT instruction */
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#define BX_CPU_AES_PCLMULQDQ (1 << 21) /* AES+PCLMULQDQ instruction */
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#define BX_CPU_MOVBE (1 << 22) /* MOVBE Intel Atom(R) instruction */
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#define BX_CPU_FSGSBASE (1 << 23) /* FS/GS BASE access instruction */
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#define BX_CPU_INVPCID (1 << 24) /* INVPCID instruction */
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#define BX_CPU_AVX (1 << 25) /* AVX instruction */
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#define BX_CPU_AVX_F16C (1 << 26) /* AVX F16 convert instruction */
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#define BX_CPU_AVX_FMA (1 << 27) /* AVX FMA instruction */
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#define BX_CPU_X86_64 (1 << 28) /* x86-64 instruction */
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#define BX_CPU_BMI (1 << 29) /* BMI instruction */
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// cpuid non-ISA features
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#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */
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#define BX_CPU_VME (1 << 1) /* VME support */
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#define BX_CPU_PSE (1 << 2) /* PSE support */
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#define BX_CPU_PAE (1 << 3) /* PAE support */
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#define BX_CPU_PGE (1 << 4) /* Global Pages support */
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#define BX_CPU_PSE36 (1 << 5) /* PSE-36 support */
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#define BX_CPU_PAT_MTRR (1 << 6) /* PAT and MTRR support */
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#define BX_CPU_XAPIC (1 << 7) /* XAPIC support */
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#define BX_CPU_X2APIC (1 << 8) /* X2APIC support */
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#define BX_CPU_1G_PAGES (1 << 9) /* 1Gb pages support */
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#define BX_CPU_PCID (1 << 10) /* PCID pages support */
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#define BX_CPU_SMEP (1 << 11) /* SMEP support */
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// CPUID defines - STD features CPUID[0x00000001].EDX
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// ----------------------------
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// [0:0] FPU on chip
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// [1:1] VME: Virtual-8086 Mode enhancements
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// [2:2] DE: Debug Extensions (I/O breakpoints)
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// [3:3] PSE: Page Size Extensions
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// [4:4] TSC: Time Stamp Counter
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// [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [16:16] PAT: Page Attribute Table
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// [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// [21:21] DS: Debug Store
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// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// [23:23] MMX Technology
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// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25:25] SSE: SSE Extensions
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// [26:26] SSE2: SSE2 Extensions
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// [27:27] Self Snoop
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// [28:28] Hyper Threading Technology
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// [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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#define BX_CPUID_STD_X87 (1 << 0)
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#define BX_CPUID_STD_VME (1 << 1)
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#define BX_CPUID_STD_DEBUG_EXTENSIONS (1 << 2)
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#define BX_CPUID_STD_PSE (1 << 3)
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#define BX_CPUID_STD_TSC (1 << 4)
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#define BX_CPUID_STD_MSR (1 << 5)
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#define BX_CPUID_STD_PAE (1 << 6)
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#define BX_CPUID_STD_MCE (1 << 7)
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#define BX_CPUID_STD_CMPXCHG8B (1 << 8)
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#define BX_CPUID_STD_APIC (1 << 9)
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#define BX_CPUID_STD_RESERVED10 (1 << 10)
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#define BX_CPUID_STD_SYSENTER_SYSEXIT (1 << 11)
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#define BX_CPUID_STD_MTRR (1 << 12)
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#define BX_CPUID_STD_GLOBAL_PAGES (1 << 13)
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#define BX_CPUID_STD_MCA (1 << 14)
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#define BX_CPUID_STD_CMOV (1 << 15)
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#define BX_CPUID_STD_PAT (1 << 16)
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#define BX_CPUID_STD_PSE36 (1 << 17)
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#define BX_CPUID_STD_PROCESSOR_SERIAL_NUMBER (1 << 18)
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#define BX_CPUID_STD_CLFLUSH (1 << 19)
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#define BX_CPUID_STD_RESERVED20 (1 << 20)
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#define BX_CPUID_STD_DEBUG_STORE (1 << 21)
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#define BX_CPUID_STD_ACPI (1 << 22)
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#define BX_CPUID_STD_MMX (1 << 23)
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#define BX_CPUID_STD_FXSAVE_FXRSTOR (1 << 24)
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#define BX_CPUID_STD_SSE (1 << 25)
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#define BX_CPUID_STD_SSE2 (1 << 26)
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#define BX_CPUID_STD_SELF_SNOOP (1 << 27)
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#define BX_CPUID_STD_HT (1 << 28)
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#define BX_CPUID_STD_THERMAL_MONITOR (1 << 29)
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#define BX_CPUID_STD_RESERVED30 (1 << 30)
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#define BX_CPUID_STD_PBE (1 << 31)
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// CPUID defines - EXT features CPUID[0x00000001].ECX
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// ----------------------------
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// [0:0] SSE3: SSE3 Instructions
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// [1:1] PCLMULQDQ Instruction support
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// [2:2] DTES64: 64-bit DS area
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// [3:3] MONITOR/MWAIT support
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// [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// [7:7] EST: Enhanced Intel SpeedStep Technology
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// [8:8] TM2: Thermal Monitor 2
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// [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// [14:14] xTPR update control
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// [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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// [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// [22:22] MOVBE instruction
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// [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// [25:25] AES Instructions
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [29:29] AVX F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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#define BX_CPUID_EXT_SSE3 (1 << 0)
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#define BX_CPUID_EXT_PCLMULQDQ (1 << 1)
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#define BX_CPUID_EXT_DTES64 (1 << 2)
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#define BX_CPUID_EXT_MONITOR_MWAIT (1 << 3)
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#define BX_CPUID_EXT_DS_CPL (1 << 4)
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#define BX_CPUID_EXT_VMX (1 << 5)
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#define BX_CPUID_EXT_SMX (1 << 6)
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#define BX_CPUID_EXT_EST (1 << 7)
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#define BX_CPUID_EXT_THERMAL_MONITOR2 (1 << 8)
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#define BX_CPUID_EXT_SSSE3 (1 << 9)
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#define BX_CPUID_EXT_CNXT_ID (1 << 10)
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#define BX_CPUID_EXT_RESERVED11 (1 << 11)
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#define BX_CPUID_EXT_FMA (1 << 12)
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#define BX_CPUID_EXT_CMPXCHG16B (1 << 13)
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#define BX_CPUID_EXT_xTPR (1 << 14)
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#define BX_CPUID_EXT_PDCM (1 << 15)
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#define BX_CPUID_EXT_RESERVED16 (1 << 16)
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#define BX_CPUID_EXT_PCID (1 << 17)
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#define BX_CPUID_EXT_DCA (1 << 18)
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#define BX_CPUID_EXT_SSE4_1 (1 << 19)
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#define BX_CPUID_EXT_SSE4_2 (1 << 20)
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#define BX_CPUID_EXT_X2APIC (1 << 21)
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#define BX_CPUID_EXT_MOVBE (1 << 22)
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#define BX_CPUID_EXT_POPCNT (1 << 23)
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#define BX_CPUID_EXT_TSC_DEADLINE (1 << 24)
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#define BX_CPUID_EXT_AES (1 << 25)
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#define BX_CPUID_EXT_XSAVE (1 << 26)
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#define BX_CPUID_EXT_OSXSAVE (1 << 27)
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#define BX_CPUID_EXT_AVX (1 << 28)
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#define BX_CPUID_EXT_AVX_F16C (1 << 29)
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#define BX_CPUID_EXT_RDRAND (1 << 30)
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#define BX_CPUID_EXT_RESERVED31 (1 << 31)
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// CPUID defines - EXT3 features CPUID[0x00000007].EBX
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// -----------------------------
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// [0:0] FS/GS BASE access instructions
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// [2:1] reserved
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// [3:3] BMI1: Advanced Bit Manipulation Extensions
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// [4:4] reserved
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// [5:5] AVX2
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// [6:6] reserved
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// [7:7] SMEP: Supervisor Mode Execution Protection
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// [8:8] BMI2: Advanced Bit Manipulation Extensions
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// [9:9] Support for Enhanced REP MOVSB/STOSB
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// [10:10] Support for INVPCID instruction
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// [31:10] reserved
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#define BX_CPUID_EXT3_FSGSBASE (1 << 0)
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#define BX_CPUID_EXT3_RESERVED1 (1 << 1)
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#define BX_CPUID_EXT3_RESERVED2 (1 << 2)
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#define BX_CPUID_EXT3_BMI1 (1 << 3)
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#define BX_CPUID_EXT3_RESERVED4 (1 << 4)
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#define BX_CPUID_EXT3_AVX2 (1 << 5)
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#define BX_CPUID_EXT3_RESERVED6 (1 << 6)
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#define BX_CPUID_EXT3_SMEP (1 << 7)
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#define BX_CPUID_EXT3_BMI2 (1 << 8)
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#define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS (1 << 9)
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#define BX_CPUID_EXT3_INVPCID (1 << 10)
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// ...
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// CPUID defines - STD2 features CPUID[0x80000001].EDX
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// -----------------------------
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// ...
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#define BX_CPUID_STD2_SYSCALL_SYSRET (1 << 11)
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// ...
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#define BX_CPUID_STD2_NX (1 << 20)
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#define BX_CPUID_STD2_RESERVED21 (1 << 21)
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#define BX_CPUID_STD2_AMD_MMX_EXT (1 << 22)
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#define BX_CPUID_STD2_RESERVED23 (1 << 23)
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#define BX_CPUID_STD2_RESERVED24 (1 << 24)
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#define BX_CPUID_STD2_FFXSR (1 << 25)
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#define BX_CPUID_STD2_1G_PAGES (1 << 26)
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#define BX_CPUID_STD2_RDTSCP (1 << 27)
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#define BX_CPUID_STD2_RESERVED28 (1 << 28)
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#define BX_CPUID_STD2_LONG_MODE (1 << 29)
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#define BX_CPUID_STD2_3DNOW_EXT (1 << 30)
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#define BX_CPUID_STD2_3DNOW (1 << 31)
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// CPUID defines - EXT2 features CPUID[0x80000001].ECX
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// -----------------------------
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// [0:0] LAHF/SAHF instructions support in 64-bit mode
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// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
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// [2:2] SVM: Secure Virtual Machine (AMD)
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// [3:3] Extended APIC Space
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// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
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// [5:5] LZCNT: LZCNT instruction support
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// [6:6] SSE4A: SSE4A Instructions support (deprecated?)
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// [7:7] Misaligned SSE support
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// [8:8] PREFETCHW: PREFETCHW instruction support
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// [9:9] OSVW: OS visible workarounds (AMD)
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// [10:10] IBS: Instruction based sampling
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// [11:11] XOP: Extended Operations Support and XOP Prefix
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// [12:12] SKINIT support
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// [13:13] WDT: Watchdog timer support
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// [14:14] reserved
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// [15:15] LWP: Light weight profiling
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// [16:16] FMA4: Four-operand FMA instructions support
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// [18:17] reserved
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// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
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// [20:20] reserved
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// [21:21] TBM: trailing bit manipulation instruction support
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// [22:22] Topology extensions support
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// [31:23] reserved
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#define BX_CPUID_EXT2_LAHF_SAHF (1 << 0)
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#define BX_CPUID_EXT2_CMP_LEGACY (1 << 1)
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#define BX_CPUID_EXT2_SVM (1 << 2)
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#define BX_CPUID_EXT2_EXT_APIC_SPACE (1 << 3)
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#define BX_CPUID_EXT2_ALT_MOV_CR8 (1 << 4)
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#define BX_CPUID_EXT2_LZCNT (1 << 5)
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#define BX_CPUID_EXT2_SSE4A (1 << 6)
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#define BX_CPUID_EXT2_MISALIGNED_SSE (1 << 7)
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#define BX_CPUID_EXT2_PREFETCHW (1 << 8)
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#define BX_CPUID_EXT2_OSVW (1 << 9)
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#define BX_CPUID_EXT2_IBS (1 << 10)
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#define BX_CPUID_EXT2_XOP (1 << 11)
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#define BX_CPUID_EXT2_SKINIT (1 << 12)
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#define BX_CPUID_EXT2_WDT (1 << 13)
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#define BX_CPUID_EXT2_RESERVED14 (1 << 14)
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#define BX_CPUID_EXT2_LWP (1 << 15)
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#define BX_CPUID_EXT2_FMA4 (1 << 16)
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#define BX_CPUID_EXT2_RESERVED17 (1 << 17)
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#define BX_CPUID_EXT2_RESERVED18 (1 << 18)
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#define BX_CPUID_EXT2_NODEID (1 << 19)
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#define BX_CPUID_EXT2_RESERVED20 (1 << 20)
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#define BX_CPUID_EXT2_TBM (1 << 21)
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#define BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS (1 << 22)
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#endif
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