50 lines
2.0 KiB
C++
50 lines
2.0 KiB
C++
extern class bx_ioapic_c bx_ioapic;
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#define BX_IOAPIC_VERSION_ID 0x00170011 // same version as 82093 IOAPIC
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#define BX_IOAPIC_NUM_PINS 0x18
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class bx_io_redirect_entry_t {
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Bit64u value;
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public:
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Bit32u get_even_word () { return value & 0xffffffff; }
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Bit32u get_odd_word () { return (value>>32) & 0xffffffff; }
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void set_even_word (Bit32u even) {
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// keep high 32 bits of value, replace low 32
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value = ((value >> 32) << 32) | (even & 0xffffffff);
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parse_value ();
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}
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void set_odd_word (Bit32u odd) {
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// keep low 32 bits of value, replace high 32
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value = (((Bit64u)odd & 0xffffffff) << 32) | (value & 0xffffffff);
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parse_value ();
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}
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void parse_value ();
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// parse_value sets the value and all the fields below. Do not change
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// these fields except by calling parse_value.
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Bit8u dest, masked, trig_mode, remote_irr, polarity, delivery_status, dest_mode, delivery_mode, vector;
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void sprintf_self (char *buf);
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};
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class bx_ioapic_c : public bx_generic_apic_c {
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Bit32u ioregsel; // selects between various registers
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// interrupt request bitmask, not visible from the outside. Bits in the
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// irr are set when trigger_irq is called, and cleared when the interrupt
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// is delivered to the processor. If an interrupt is masked, the irr
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// will still be set but delivery will not occur until it is unmasked.
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// It's not clear if this is how the real device works.
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Bit32u irr;
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public:
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bx_io_redirect_entry_t ioredtbl[BX_IOAPIC_NUM_PINS]; // table of redirections
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bx_ioapic_c ();
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~bx_ioapic_c ();
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virtual void init ();
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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virtual void write(Bit32u address, Bit32u *value, unsigned len);
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void trigger_irq (unsigned num, unsigned from);
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void untrigger_irq (unsigned num, unsigned from);
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void service_ioapic ();
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virtual Boolean match_logical_addr (Bit8u address) { return false; }
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virtual Boolean is_local_apic () { return false; }
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virtual bx_apic_type_t get_type () { return APIC_TYPE_IOAPIC; }
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};
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