b84f0bd0f2
there to offer a way to substitute more efficient code to do the RMW cases. At the moment, they just map to the normal functions. Sorry, restored the previous version ...
390 lines
8.6 KiB
C++
390 lines
8.6 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer16.cc,v 1.20 2002-10-25 18:26:27 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::MOV_RXIw(bxInstruction_c *i)
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{
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx = i->Iw();
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}
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void
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BX_CPU_C::XCHG_RXAX(bxInstruction_c *i)
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{
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Bit16u temp16;
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temp16 = AX;
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AX = BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx;
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx = temp16;
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}
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void
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BX_CPU_C::MOV_EEwGw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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write_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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void
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BX_CPU_C::MOV_EGwGw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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BX_WRITE_16BIT_REG(i->rm(), op2_16);
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}
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void
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BX_CPU_C::MOV_GwEGw(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a general register Gw.
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Bit16u op2_16;
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op2_16 = BX_READ_16BIT_REG(i->rm());
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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}
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void
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BX_CPU_C::MOV_GwEEw(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a memory operand, Ew.
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Bit16u op2_16;
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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}
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void
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BX_CPU_C::MOV_EwSw(bxInstruction_c *i)
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{
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Bit16u seg_reg;
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOV_EwSw: incomplete for CPU < 3"));
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#endif
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seg_reg = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value;
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if (i->modC0()) {
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// ??? BX_WRITE_16BIT_REG(mem_addr, seg_reg);
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if ( i->os32L() ) {
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BX_WRITE_32BIT_REGZ(i->rm(), seg_reg);
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}
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else {
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BX_WRITE_16BIT_REG(i->rm(), seg_reg);
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}
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}
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else {
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write_virtual_word(i->seg(), RMAddr(i), &seg_reg);
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}
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}
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void
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BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOV_SwEw: incomplete for CPU < 3"));
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#endif
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], op2_16);
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if (i->nnn() == BX_SEG_REG_SS) {
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// MOV SS inhibits interrupts, debug exceptions and single-step
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// trap exceptions until the execution boundary following the
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// next instruction is reached.
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// Same code as POP_SS()
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BX_CPU_THIS_PTR inhibit_mask |=
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BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
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BX_CPU_THIS_PTR async_event = 1;
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}
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}
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void
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BX_CPU_C::LEA_GwM(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_PANIC(("LEA_GvM: op2 is a register"));
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UndefinedOpcode(i);
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return;
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}
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BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) RMAddr(i));
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}
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void
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BX_CPU_C::MOV_AXOw(bxInstruction_c *i)
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{
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Bit16u temp_16;
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bx_address addr;
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addr = i->Id();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_word(i->seg(), addr, &temp_16);
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}
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else {
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read_virtual_word(BX_SEG_REG_DS, addr, &temp_16);
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}
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/* write to register */
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AX = temp_16;
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}
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void
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BX_CPU_C::MOV_OwAX(bxInstruction_c *i)
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{
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Bit16u temp_16;
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bx_address addr;
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addr = i->Id();
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/* read from register */
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temp_16 = AX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_word(i->seg(), addr, &temp_16);
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}
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else {
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write_virtual_word(BX_SEG_REG_DS, addr, &temp_16);
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}
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}
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void
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BX_CPU_C::MOV_EwIw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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op2_16 = i->Iw();
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/* now write sum back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), op2_16);
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}
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else {
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write_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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}
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void
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BX_CPU_C::MOVZX_GwEb(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVZX_GvEb: not supported on < 386"));
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#else
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Bit8u op2_8;
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if (i->modC0()) {
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op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
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}
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/* zero extend byte op2 into word op1 */
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BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) op2_8);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::MOVZX_GwEw(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVZX_GvEw: not supported on < 386"));
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#else
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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/* normal move */
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::MOVSX_GwEb(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVSX_GvEb: not supported on < 386"));
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#else
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Bit8u op2_8;
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if (i->modC0()) {
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op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
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}
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/* sign extend byte op2 into word op1 */
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BX_WRITE_16BIT_REG(i->nnn(), (Bit8s) op2_8);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::MOVSX_GwEw(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVSX_GvEw: not supported on < 386"));
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#else
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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/* normal move */
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::XCHG_EwGw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16;
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#ifdef MAGIC_BREAKPOINT
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#if BX_DEBUGGER
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// (mch) Magic break point
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if (i->nnn() == 3 && i->modC0() && i->rm() == 3) {
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BX_CPU_THIS_PTR magic_break = 1;
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}
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#endif
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#endif
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/* op2_16 is a register, op2_addr is an index of a register */
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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/* op1_16 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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BX_WRITE_16BIT_REG(i->rm(), op2_16);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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Write_RMW_virtual_word(op2_16);
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}
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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}
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void
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BX_CPU_C::CMOV_GwEw(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6)
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// Note: CMOV accesses a memory source operand (read), regardless
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// of whether condition is true or not. Thus, exceptions may
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// occur even if the MOV does not take place.
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bx_bool condition;
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Bit16u op2_16;
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switch (i->b1()) {
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// CMOV opcodes:
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case 0x140: condition = get_OF(); break;
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case 0x141: condition = !get_OF(); break;
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case 0x142: condition = get_CF(); break;
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case 0x143: condition = !get_CF(); break;
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case 0x144: condition = get_ZF(); break;
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case 0x145: condition = !get_ZF(); break;
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case 0x146: condition = get_CF() || get_ZF(); break;
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case 0x147: condition = !get_CF() && !get_ZF(); break;
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case 0x148: condition = get_SF(); break;
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case 0x149: condition = !get_SF(); break;
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case 0x14A: condition = get_PF(); break;
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case 0x14B: condition = !get_PF(); break;
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case 0x14C: condition = getB_SF() != getB_OF(); break;
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case 0x14D: condition = getB_SF() == getB_OF(); break;
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case 0x14E: condition = get_ZF() || (getB_SF() != getB_OF()); break;
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case 0x14F: condition = !get_ZF() && (getB_SF() == getB_OF()); break;
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default:
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condition = 0;
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BX_PANIC(("CMOV_GwEw: default case"));
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}
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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if (condition) {
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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}
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#else
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BX_INFO(("cmov_gwew called"));
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UndefinedOpcode(i);
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#endif
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}
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