493 lines
15 KiB
C++
493 lines
15 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "cpu.h"
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#include "athlon64_venice.h"
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#define LOG_THIS cpu->
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#if BX_SUPPORT_X86_64
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athlon64_venice_t::athlon64_venice_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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{
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if (! BX_SUPPORT_X86_64)
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BX_PANIC(("You must enable x86-64 for Athlon64 configuration"));
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BX_INFO(("WARNING: 3DNow! is not implemented yet !"));
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}
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void athlon64_venice_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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{
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switch(function) {
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case 0x8FFFFFFF:
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get_cpuid_hidden_level(leaf);
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return;
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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get_ext_cpuid_brand_string_leaf(function, leaf);
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return;
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case 0x80000005:
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get_ext_cpuid_leaf_5(leaf);
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return;
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case 0x80000006:
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get_ext_cpuid_leaf_6(leaf);
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return;
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case 0x80000007:
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get_ext_cpuid_leaf_7(leaf);
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return;
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case 0x80000008:
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get_ext_cpuid_leaf_8(leaf);
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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default:
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get_reserved_leaf(leaf);
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return;
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}
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}
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Bit64u athlon64_venice_t::get_isa_extensions_bitmask(void) const
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{
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return BX_ISA_X87 |
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BX_ISA_486 |
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BX_ISA_PENTIUM |
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BX_ISA_P6 |
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BX_ISA_MMX |
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BX_ISA_3DNOW |
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BX_ISA_SYSCALL_SYSRET_LEGACY |
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BX_ISA_SYSENTER_SYSEXIT |
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BX_ISA_CLFLUSH |
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BX_ISA_SSE |
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BX_ISA_SSE2 |
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BX_ISA_SSE3 |
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BX_ISA_LM_LAHF_SAHF;
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}
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Bit32u athlon64_venice_t::get_cpu_extensions_bitmask(void) const
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{
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return BX_CPU_DEBUG_EXTENSIONS |
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BX_CPU_VME |
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BX_CPU_PSE |
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BX_CPU_PAE |
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BX_CPU_PGE |
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BX_CPU_PSE36 |
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BX_CPU_MTRR |
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BX_CPU_PAT |
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BX_CPU_XAPIC |
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BX_CPU_LONG_MODE |
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BX_CPU_NX |
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BX_CPU_FFXSR;
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}
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// leaf 0x00000000 //
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void athlon64_venice_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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static const char* vendor_string = "AuthenticAMD";
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// EAX: highest std function understood by CPUID
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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leaf->eax = 0x1;
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// CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
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memcpy(&(leaf->ebx), vendor_string, 4);
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memcpy(&(leaf->edx), vendor_string + 4, 4);
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memcpy(&(leaf->ecx), vendor_string + 8, 4);
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#ifdef BX_BIG_ENDIAN
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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// leaf 0x00000001 //
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void athlon64_venice_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x00020FF2;
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// EBX:
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// [7:0] Brand ID
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// [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8);
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#if BX_SUPPORT_APIC
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leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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// * [0:0] SSE3: SSE3 Instructions
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// [1:1] PCLMULQDQ Instruction support
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// [2:2] DTES64: 64-bit DS area
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// [3:3] MONITOR/MWAIT support
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// [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// [7:7] EST: Enhanced Intel SpeedStep Technology
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// [8:8] TM2: Thermal Monitor 2
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// [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// [14:14] xTPR update control
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// [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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// [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// [22:22] MOVBE instruction
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// [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// [25:25] AES Instructions
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [29:29] AVX F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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leaf->ecx = BX_CPUID_EXT_SSE3;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSENTER/SYSEXIT support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// * [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// * [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// [21:21] DS: Debug Store
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// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] SSE: SSE Extensions
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// * [26:26] SSE2: SSE2 Extensions
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// [27:27] Self Snoop
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// [28:28] Hyper Threading Technology
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// [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD_SYSENTER_SYSEXIT |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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BX_CPUID_STD_PSE36 |
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BX_CPUID_STD_CLFLUSH |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD_SSE |
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BX_CPUID_STD_SSE2;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x80000000 //
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void athlon64_venice_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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static const char* vendor_string = "AuthenticAMD";
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// EAX: highest extended function understood by CPUID
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// EBX: reserved
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// EDX: reserved
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// ECX: reserved
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leaf->eax = 0x80000018;
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memcpy(&(leaf->ebx), vendor_string, 4);
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memcpy(&(leaf->edx), vendor_string + 4, 4);
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memcpy(&(leaf->ecx), vendor_string + 8, 4);
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#ifdef BX_BIG_ENDIAN
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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// leaf 0x80000001 //
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void athlon64_venice_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information (same as 0x00000001.EAX)
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leaf->eax = 0x00020FF2;
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// EBX: Brand ID
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leaf->ebx = 0x00000108;
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// ECX:
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// * [0:0] LAHF/SAHF instructions support in 64-bit mode
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// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
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// [2:2] SVM: Secure Virtual Machine (AMD)
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// [3:3] Extended APIC Space
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// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
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// [5:5] LZCNT: LZCNT instruction support
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// [6:6] SSE4A: SSE4A Instructions support
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// [7:7] Misaligned SSE support
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// [8:8] PREFETCHW: PREFETCHW instruction support
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// [9:9] OSVW: OS visible workarounds (AMD)
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// [11:10] reserved
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// [12:12] SKINIT support
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// [13:13] WDT: Watchdog timer support
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// [31:14] reserved
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leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF;
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// EDX:
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// Many of the bits in EDX are the same as FN 0x00000001 for AMD
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSCALL/SYSRET support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// * [17:17] PSE-36: Physical Address Extensions
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// [18:18] Reserved
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// [19:19] Reserved
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// * [20:20] No-Execute page protection
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// [21:21] Reserved
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// * [22:22] AMD MMX Extensions
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] Fast FXSAVE/FXRSTOR mode support
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// [26:26] 1G paging support
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// [27:27] Support RDTSCP Instruction
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// [28:28] Reserved
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// * [29:29] Long Mode
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// * [30:30] AMD 3DNow! Extensions
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// * [31:31] AMD 3DNow! Instructions
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD2_SYSCALL_SYSRET |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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BX_CPUID_STD_PSE36 |
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BX_CPUID_STD2_NX |
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BX_CPUID_STD2_AMD_MMX_EXT |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD2_FFXSR |
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BX_CPUID_STD2_LONG_MODE |
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BX_CPUID_STD2_3DNOW_EXT |
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BX_CPUID_STD2_3DNOW;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x80000002 //
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// leaf 0x80000003 //
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// leaf 0x80000004 //
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void athlon64_venice_t::get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const
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{
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// CPUID function 0x80000002-0x80000004 - Processor Name String Identifier
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static const char* brand_string = "AMD Athlon(tm) 64 Processor 3000+\0\0\0";
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switch(function) {
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case 0x80000002:
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memcpy(&(leaf->eax), brand_string , 4);
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memcpy(&(leaf->ebx), brand_string + 4, 4);
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memcpy(&(leaf->ecx), brand_string + 8, 4);
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memcpy(&(leaf->edx), brand_string + 12, 4);
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break;
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case 0x80000003:
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memcpy(&(leaf->eax), brand_string + 16, 4);
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memcpy(&(leaf->ebx), brand_string + 20, 4);
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memcpy(&(leaf->ecx), brand_string + 24, 4);
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memcpy(&(leaf->edx), brand_string + 28, 4);
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break;
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case 0x80000004:
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memcpy(&(leaf->eax), brand_string + 32, 4);
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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break;
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default:
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break;
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}
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#ifdef BX_BIG_ENDIAN
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leaf->eax = bx_bswap32(leaf->eax);
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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// leaf 0x80000005 //
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void athlon64_venice_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const
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{
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// CPUID function 0x800000005 - L1 Cache and TLB Identifiers
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leaf->eax = 0xFF08FF08;
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leaf->ebx = 0xFF20FF20;
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leaf->ecx = 0x40020140;
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leaf->edx = 0x40020140;
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}
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// leaf 0x80000006 //
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void athlon64_venice_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const
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{
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// CPUID function 0x800000006 - L2 Cache and TLB Identifiers
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leaf->eax = 0x00000000;
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leaf->ebx = 0x42004200;
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leaf->ecx = 0x02008140;
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leaf->edx = 0x00000000;
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}
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// leaf 0x80000007 //
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void athlon64_venice_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const
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{
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// CPUID function 0x800000007 - Advanced Power Management
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0x0000003F;
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}
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// leaf 0x80000008 //
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void athlon64_venice_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const
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{
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// virtual & phys address size in low 2 bytes.
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leaf->eax = BX_PHY_ADDRESS_WIDTH | (BX_LIN_ADDRESS_WIDTH << 8);
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0; // Reserved, undefined
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
// leaf 0x80000009 : Reserved //
|
|
// leaf 0x8000000A : SVM //
|
|
// leaf 0x8000000B - 0x80000018: Reserved //
|
|
|
|
// leaf 0x8FFFFFFF //
|
|
void athlon64_venice_t::get_cpuid_hidden_level(cpuid_function_t *leaf) const
|
|
{
|
|
static const char* magic_string = "IT'S HAMMER TIME";
|
|
|
|
memcpy(&(leaf->eax), magic_string , 4);
|
|
memcpy(&(leaf->ebx), magic_string + 4, 4);
|
|
memcpy(&(leaf->ecx), magic_string + 8, 4);
|
|
memcpy(&(leaf->edx), magic_string + 12, 4);
|
|
|
|
#ifdef BX_BIG_ENDIAN
|
|
leaf->eax = bx_bswap32(leaf->eax);
|
|
leaf->ebx = bx_bswap32(leaf->ebx);
|
|
leaf->ecx = bx_bswap32(leaf->ecx);
|
|
leaf->edx = bx_bswap32(leaf->edx);
|
|
#endif
|
|
}
|
|
|
|
void athlon64_venice_t::dump_cpuid(void) const
|
|
{
|
|
struct cpuid_function_t leaf;
|
|
unsigned n;
|
|
|
|
for (n=0; n<=1; n++) {
|
|
get_cpuid_leaf(n, 0x00000000, &leaf);
|
|
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
|
}
|
|
|
|
for (n=0x80000000; n<=0x80000018; n++) {
|
|
get_cpuid_leaf(n, 0x00000000, &leaf);
|
|
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
|
}
|
|
|
|
get_cpuid_leaf(0x8fffffff, 0x00000000, &leaf);
|
|
BX_INFO(("CPUID[0x8fffffff]: %08x %08x %08x %08x", leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
|
}
|
|
|
|
bx_cpuid_t *create_athlon64_venice_cpuid(BX_CPU_C *cpu) { return new athlon64_venice_t(cpu); }
|
|
|
|
#endif
|