476 lines
16 KiB
C++
476 lines
16 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2004-2014 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// PCI IDE controller
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// i430FX - PIIX
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// i440FX - PIIX3
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI
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#include "pci.h"
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#include "pci_ide.h"
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#define LOG_THIS thePciIdeController->
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bx_pci_ide_c *thePciIdeController = NULL;
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const Bit8u bmdma_iomask[16] = {1, 0, 1, 0, 4, 0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0};
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int libpci_ide_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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thePciIdeController = new bx_pci_ide_c();
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bx_devices.pluginPciIdeController = thePciIdeController;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePciIdeController, BX_PLUGIN_PCI_IDE);
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return(0); // Success
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}
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void libpci_ide_LTX_plugin_fini(void)
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{
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delete thePciIdeController;
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}
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bx_pci_ide_c::bx_pci_ide_c()
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{
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put("pci_ide", "PIDE");
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s.bmdma[0].timer_index = BX_NULL_TIMER_HANDLE;
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s.bmdma[1].timer_index = BX_NULL_TIMER_HANDLE;
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s.bmdma[0].buffer = NULL;
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s.bmdma[1].buffer = NULL;
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}
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bx_pci_ide_c::~bx_pci_ide_c()
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{
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if (s.bmdma[0].buffer != NULL) {
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delete [] s.bmdma[0].buffer;
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}
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if (s.bmdma[1].buffer != NULL) {
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delete [] s.bmdma[1].buffer;
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}
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SIM->get_bochs_root()->remove("pci_ide");
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BX_DEBUG(("Exit"));
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}
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void bx_pci_ide_c::init(void)
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{
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unsigned i;
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Bit8u devfunc = BX_PCI_DEVICE(1,1);
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DEV_register_pci_handlers(this, &devfunc,
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BX_PLUGIN_PCI_IDE, "PIIX3 PCI IDE controller");
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// register BM-DMA timer
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for (i=0; i<2; i++) {
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if (BX_PIDE_THIS s.bmdma[i].timer_index == BX_NULL_TIMER_HANDLE) {
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BX_PIDE_THIS s.bmdma[i].timer_index =
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DEV_register_timer(this, timer_handler, 1000, 0,0, "PIIX3 BM-DMA timer");
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bx_pc_system.setTimerParam(BX_PIDE_THIS s.bmdma[i].timer_index, i);
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}
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}
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BX_PIDE_THIS s.bmdma[0].buffer = new Bit8u[0x20000];
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BX_PIDE_THIS s.bmdma[1].buffer = new Bit8u[0x20000];
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BX_PIDE_THIS s.chipset = SIM->get_param_enum(BXPN_PCI_CHIPSET)->get();
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// initialize readonly registers
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if (BX_PIDE_THIS s.chipset == BX_PCI_CHIPSET_I440FX) {
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init_pci_conf(0x8086, 0x7010, 0x00, 0x010180, 0x00);
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} else {
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init_pci_conf(0x8086, 0x1230, 0x00, 0x010180, 0x00);
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}
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BX_PIDE_THIS pci_conf[0x20] = 0x01;
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BX_PIDE_THIS pci_base_address[4] = 0;
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}
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void bx_pci_ide_c::reset(unsigned type)
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{
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BX_PIDE_THIS pci_conf[0x04] = 0x01;
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BX_PIDE_THIS pci_conf[0x06] = 0x80;
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BX_PIDE_THIS pci_conf[0x07] = 0x02;
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if (SIM->get_param_bool(BXPN_ATA0_ENABLED)->get()) {
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BX_PIDE_THIS pci_conf[0x40] = 0x00;
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BX_PIDE_THIS pci_conf[0x41] = 0x80;
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}
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if (SIM->get_param_bool(BXPN_ATA1_ENABLED)->get()) {
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BX_PIDE_THIS pci_conf[0x42] = 0x00;
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BX_PIDE_THIS pci_conf[0x43] = 0x80;
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}
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BX_PIDE_THIS pci_conf[0x44] = 0x00;
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for (unsigned i=0; i<2; i++) {
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BX_PIDE_THIS s.bmdma[i].cmd_ssbm = 0;
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BX_PIDE_THIS s.bmdma[i].cmd_rwcon = 0;
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BX_PIDE_THIS s.bmdma[i].status = 0;
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BX_PIDE_THIS s.bmdma[i].dtpr = 0;
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BX_PIDE_THIS s.bmdma[i].prd_current = 0;
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BX_PIDE_THIS s.bmdma[i].buffer_top = BX_PIDE_THIS s.bmdma[i].buffer;
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BX_PIDE_THIS s.bmdma[i].buffer_idx = BX_PIDE_THIS s.bmdma[i].buffer;
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BX_PIDE_THIS s.bmdma[i].data_ready = 0;
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}
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}
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// save/restore code begin
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void bx_pci_ide_c::register_state(void)
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{
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char name[6];
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci_ide", "PCI IDE Controller State");
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register_pci_state(list);
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new bx_shadow_data_c(list, "buffer0", BX_PIDE_THIS s.bmdma[0].buffer, 0x20000);
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new bx_shadow_data_c(list, "buffer1", BX_PIDE_THIS s.bmdma[1].buffer, 0x20000);
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for (unsigned i=0; i<2; i++) {
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sprintf(name, "%d", i);
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bx_list_c *ctrl = new bx_list_c(list, name);
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BXRS_PARAM_BOOL(ctrl, cmd_ssbm, BX_PIDE_THIS s.bmdma[i].cmd_ssbm);
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BXRS_PARAM_BOOL(ctrl, cmd_rwcon, BX_PIDE_THIS s.bmdma[i].cmd_rwcon);
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BXRS_HEX_PARAM_FIELD(ctrl, status, BX_PIDE_THIS s.bmdma[i].status);
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BXRS_HEX_PARAM_FIELD(ctrl, dtpr, BX_PIDE_THIS s.bmdma[i].dtpr);
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BXRS_HEX_PARAM_FIELD(ctrl, prd_current, BX_PIDE_THIS s.bmdma[i].prd_current);
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BXRS_PARAM_SPECIAL32(ctrl, buffer_top,
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BX_PIDE_THIS param_save_handler, BX_PIDE_THIS param_restore_handler);
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BXRS_PARAM_SPECIAL32(ctrl, buffer_idx,
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BX_PIDE_THIS param_save_handler, BX_PIDE_THIS param_restore_handler);
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BXRS_PARAM_BOOL(ctrl, data_ready, BX_PIDE_THIS s.bmdma[i].data_ready);
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}
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}
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void bx_pci_ide_c::after_restore_state(void)
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{
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if (DEV_pci_set_base_io(BX_PIDE_THIS_PTR, read_handler, write_handler,
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&BX_PIDE_THIS pci_base_address[4], &BX_PIDE_THIS pci_conf[0x20],
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16, &bmdma_iomask[0], "PIIX3 PCI IDE controller"))
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{
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BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS pci_base_address[4]));
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}
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}
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Bit64s bx_pci_ide_c::param_save_handler(void *devptr, bx_param_c *param)
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{
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#if !BX_USE_PIDE_SMF
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bx_pci_ide_c *class_ptr = (bx_pci_ide_c *) devptr;
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return class_ptr->param_save(param, val);
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}
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Bit64s bx_pci_ide_c::param_save(bx_param_c *param)
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{
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#else
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UNUSED(devptr);
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#endif // !BX_USE_PIDE_SMF
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int chan = atoi(param->get_parent()->get_name());
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Bit64s val = 0;
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if (!strcmp(param->get_name(), "buffer_top")) {
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val = (Bit32u)(BX_PIDE_THIS s.bmdma[chan].buffer_top - BX_PIDE_THIS s.bmdma[chan].buffer);
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} else if (!strcmp(param->get_name(), "buffer_idx")) {
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val = (Bit32u)(BX_PIDE_THIS s.bmdma[chan].buffer_idx - BX_PIDE_THIS s.bmdma[chan].buffer);
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}
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return val;
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}
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void bx_pci_ide_c::param_restore_handler(void *devptr, bx_param_c *param, Bit64s val)
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{
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#if !BX_USE_PIDE_SMF
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bx_pci_ide_c *class_ptr = (bx_pci_ide_c *) devptr;
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class_ptr->param_restore(param, val);
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}
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void bx_pci_ide_c::param_restore(bx_param_c *param, Bit64s val)
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{
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#else
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UNUSED(devptr);
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#endif // !BX_USE_PIDE_SMF
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int chan = atoi(param->get_parent()->get_name());
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if (!strcmp(param->get_name(), "buffer_top")) {
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BX_PIDE_THIS s.bmdma[chan].buffer_top = BX_PIDE_THIS s.bmdma[chan].buffer + val;
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} else if (!strcmp(param->get_name(), "buffer_idx")) {
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BX_PIDE_THIS s.bmdma[chan].buffer_idx = BX_PIDE_THIS s.bmdma[chan].buffer + val;
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}
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}
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// save/restore code end
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bx_bool bx_pci_ide_c::bmdma_present(void)
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{
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return (BX_PIDE_THIS pci_base_address[4] > 0);
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}
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void bx_pci_ide_c::bmdma_start_transfer(Bit8u channel)
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{
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if (channel < 2) {
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BX_PIDE_THIS s.bmdma[channel].data_ready = 1;
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}
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}
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void bx_pci_ide_c::bmdma_set_irq(Bit8u channel)
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{
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if (channel < 2) {
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BX_PIDE_THIS s.bmdma[channel].status |= 0x04;
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}
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}
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void bx_pci_ide_c::timer_handler(void *this_ptr)
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{
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bx_pci_ide_c *class_ptr = (bx_pci_ide_c *) this_ptr;
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class_ptr->timer();
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}
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void bx_pci_ide_c::timer()
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{
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int count;
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Bit32u size, sector_size;
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struct {
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Bit32u addr;
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Bit32u size;
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} prd;
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Bit8u channel = bx_pc_system.triggeredTimerParam();
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if (((BX_PIDE_THIS s.bmdma[channel].status & 0x01) == 0) ||
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(BX_PIDE_THIS s.bmdma[channel].prd_current == 0)) {
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return;
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}
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if (BX_PIDE_THIS s.bmdma[channel].cmd_rwcon &&
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!BX_PIDE_THIS s.bmdma[channel].data_ready) {
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bx_pc_system.activate_timer(BX_PIDE_THIS s.bmdma[channel].timer_index, 1000, 0);
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return;
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}
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DEV_MEM_READ_PHYSICAL(BX_PIDE_THIS s.bmdma[channel].prd_current, 4, (Bit8u *)&prd.addr);
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DEV_MEM_READ_PHYSICAL(BX_PIDE_THIS s.bmdma[channel].prd_current+4, 4, (Bit8u *)&prd.size);
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size = prd.size & 0xfffe;
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if (size == 0) {
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size = 0x10000;
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}
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if (BX_PIDE_THIS s.bmdma[channel].cmd_rwcon) {
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BX_DEBUG(("READ DMA to addr=0x%08x, size=0x%08x", prd.addr, size));
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count = size - (BX_PIDE_THIS s.bmdma[channel].buffer_top - BX_PIDE_THIS s.bmdma[channel].buffer_idx);
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while (count > 0) {
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sector_size = count;
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if (DEV_hd_bmdma_read_sector(channel, BX_PIDE_THIS s.bmdma[channel].buffer_top, §or_size)) {
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BX_PIDE_THIS s.bmdma[channel].buffer_top += sector_size;
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count -= sector_size;
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} else {
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break;
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}
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};
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if (count > 0) {
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BX_PIDE_THIS s.bmdma[channel].status &= ~0x01;
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BX_PIDE_THIS s.bmdma[channel].status |= 0x06;
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return;
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} else {
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DEV_MEM_WRITE_PHYSICAL_DMA(prd.addr, size, BX_PIDE_THIS s.bmdma[channel].buffer_idx);
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BX_PIDE_THIS s.bmdma[channel].buffer_idx += size;
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}
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} else {
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BX_DEBUG(("WRITE DMA from addr=0x%08x, size=0x%08x", prd.addr, size));
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DEV_MEM_READ_PHYSICAL_DMA(prd.addr, size, BX_PIDE_THIS s.bmdma[channel].buffer_top);
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BX_PIDE_THIS s.bmdma[channel].buffer_top += size;
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count = BX_PIDE_THIS s.bmdma[channel].buffer_top - BX_PIDE_THIS s.bmdma[channel].buffer_idx;
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while (count > 511) {
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if (DEV_hd_bmdma_write_sector(channel, BX_PIDE_THIS s.bmdma[channel].buffer_idx)) {
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BX_PIDE_THIS s.bmdma[channel].buffer_idx += 512;
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count -= 512;
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} else {
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break;
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}
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};
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if (count > 511) {
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BX_PIDE_THIS s.bmdma[channel].status &= ~0x01;
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BX_PIDE_THIS s.bmdma[channel].status |= 0x06;
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return;
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}
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}
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if (prd.size & 0x80000000) {
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BX_PIDE_THIS s.bmdma[channel].status &= ~0x01;
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BX_PIDE_THIS s.bmdma[channel].status |= 0x04;
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BX_PIDE_THIS s.bmdma[channel].prd_current = 0;
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DEV_hd_bmdma_complete(channel);
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} else {
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// To avoid buffer overflow reset buffer pointers and copy data if necessary
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count = BX_PIDE_THIS s.bmdma[channel].buffer_top - BX_PIDE_THIS s.bmdma[channel].buffer_idx;
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if (count > 0) {
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memcpy(BX_PIDE_THIS s.bmdma[channel].buffer, BX_PIDE_THIS s.bmdma[channel].buffer_idx, count);
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}
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BX_PIDE_THIS s.bmdma[channel].buffer_top = BX_PIDE_THIS s.bmdma[channel].buffer + count;
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BX_PIDE_THIS s.bmdma[channel].buffer_idx = BX_PIDE_THIS s.bmdma[channel].buffer;
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// Prepare for next PRD
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BX_PIDE_THIS s.bmdma[channel].prd_current += 8;
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DEV_MEM_READ_PHYSICAL(BX_PIDE_THIS s.bmdma[channel].prd_current, 4, (Bit8u *)&prd.addr);
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DEV_MEM_READ_PHYSICAL(BX_PIDE_THIS s.bmdma[channel].prd_current+4, 4, (Bit8u *)&prd.size);
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size = prd.size & 0xfffe;
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if (size == 0) {
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size = 0x10000;
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}
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bx_pc_system.activate_timer(BX_PIDE_THIS s.bmdma[channel].timer_index, (size >> 4) | 0x10, 0);
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}
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u bx_pci_ide_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_PIDE_SMF
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bx_pci_ide_c *class_ptr = (bx_pci_ide_c *) this_ptr;
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return class_ptr->read(address, io_len);
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}
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Bit32u bx_pci_ide_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PIDE_SMF
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Bit8u offset, channel;
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Bit32u value = 0xffffffff;
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offset = address - BX_PIDE_THIS pci_base_address[4];
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channel = (offset >> 3);
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offset &= 0x07;
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switch (offset) {
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case 0x00:
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value = BX_PIDE_THIS s.bmdma[channel].cmd_ssbm |
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(BX_PIDE_THIS s.bmdma[channel].cmd_rwcon << 3);
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BX_DEBUG(("BM-DMA read command register, channel %d, value = 0x%02x", channel, value));
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break;
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case 0x02:
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value = BX_PIDE_THIS s.bmdma[channel].status;
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BX_DEBUG(("BM-DMA read status register, channel %d, value = 0x%02x", channel, value));
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break;
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case 0x04:
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value = BX_PIDE_THIS s.bmdma[channel].dtpr;
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BX_DEBUG(("BM-DMA read DTP register, channel %d, value = 0x%04x", channel, value));
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break;
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}
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return value;
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void bx_pci_ide_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PIDE_SMF
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bx_pci_ide_c *class_ptr = (bx_pci_ide_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void bx_pci_ide_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PIDE_SMF
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Bit8u offset, channel;
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offset = address - BX_PIDE_THIS pci_base_address[4];
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channel = (offset >> 3);
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offset &= 0x07;
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switch (offset) {
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case 0x00:
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BX_DEBUG(("BM-DMA write command register, channel %d, value = 0x%02x", channel, value));
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BX_PIDE_THIS s.bmdma[channel].cmd_rwcon = (value >> 3) & 1;
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if ((value & 0x01) && !BX_PIDE_THIS s.bmdma[channel].cmd_ssbm) {
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BX_PIDE_THIS s.bmdma[channel].cmd_ssbm = 1;
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BX_PIDE_THIS s.bmdma[channel].status |= 0x01;
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BX_PIDE_THIS s.bmdma[channel].prd_current = BX_PIDE_THIS s.bmdma[channel].dtpr;
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BX_PIDE_THIS s.bmdma[channel].buffer_top = BX_PIDE_THIS s.bmdma[channel].buffer;
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BX_PIDE_THIS s.bmdma[channel].buffer_idx = BX_PIDE_THIS s.bmdma[channel].buffer;
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BX_PIDE_THIS s.bmdma[channel].data_ready = 0;
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bx_pc_system.activate_timer(BX_PIDE_THIS s.bmdma[channel].timer_index, 1000, 0);
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} else if (!(value & 0x01) && BX_PIDE_THIS s.bmdma[channel].cmd_ssbm) {
|
|
BX_PIDE_THIS s.bmdma[channel].cmd_ssbm = 0;
|
|
BX_PIDE_THIS s.bmdma[channel].status &= ~0x01;
|
|
}
|
|
break;
|
|
case 0x02:
|
|
BX_PIDE_THIS s.bmdma[channel].status = (value & 0x60)
|
|
| (BX_PIDE_THIS s.bmdma[channel].status & 0x01)
|
|
| (BX_PIDE_THIS s.bmdma[channel].status & (~value & 0x06));
|
|
BX_DEBUG(("BM-DMA write status register, channel %d, value = 0x%02x", channel, value));
|
|
break;
|
|
case 0x04:
|
|
BX_PIDE_THIS s.bmdma[channel].dtpr = value & 0xfffffffc;
|
|
BX_DEBUG(("BM-DMA write DTP register, channel %d, value = 0x%04x", channel, value));
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
// pci configuration space read callback handler
|
|
Bit32u bx_pci_ide_c::pci_read_handler(Bit8u address, unsigned io_len)
|
|
{
|
|
Bit32u value = 0;
|
|
|
|
for (unsigned i=0; i<io_len; i++) {
|
|
value |= (BX_PIDE_THIS pci_conf[address+i] << (i*8));
|
|
}
|
|
BX_DEBUG(("PIIX3 PCI IDE read register 0x%02x value 0x%08x", address, value));
|
|
return value;
|
|
}
|
|
|
|
// pci configuration space write callback handler
|
|
void bx_pci_ide_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
|
|
{
|
|
Bit8u value8, oldval;
|
|
bx_bool bmdma_change = 0;
|
|
|
|
if (((address >= 0x10) && (address < 0x20)) ||
|
|
((address > 0x23) && (address < 0x40)))
|
|
return;
|
|
for (unsigned i=0; i<io_len; i++) {
|
|
oldval = BX_PIDE_THIS pci_conf[address+i];
|
|
value8 = (value >> (i*8)) & 0xFF;
|
|
switch (address+i) {
|
|
case 0x05:
|
|
case 0x06:
|
|
break;
|
|
case 0x04:
|
|
BX_PIDE_THIS pci_conf[address+i] = value8 & 0x05;
|
|
break;
|
|
case 0x20:
|
|
value8 = (value8 & 0xfc) | 0x01;
|
|
case 0x21:
|
|
case 0x22:
|
|
case 0x23:
|
|
bmdma_change |= (value8 != oldval);
|
|
default:
|
|
BX_PIDE_THIS pci_conf[address+i] = value8;
|
|
BX_DEBUG(("PIIX3 PCI IDE write register 0x%02x value 0x%02x", address+i,
|
|
value8));
|
|
}
|
|
}
|
|
if (bmdma_change) {
|
|
if (DEV_pci_set_base_io(BX_PIDE_THIS_PTR, read_handler, write_handler,
|
|
&BX_PIDE_THIS pci_base_address[4], &BX_PIDE_THIS pci_conf[0x20],
|
|
16, &bmdma_iomask[0], "PIIX3 PCI IDE controller")) {
|
|
BX_INFO(("new BM-DMA address: 0x%04x", BX_PIDE_THIS pci_base_address[4]));
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif /* BX_SUPPORT_PCI */
|