402d02974d
in cpu.cc out of the main loop, and into the asynchronous
events handling. I went through all the code paths, and
there doesn't seem to be any reason for that code to be
in the hot loop.
Added another accessor for getting instruction data, called
modC0(). A lot of instructions test whether the mod field
of mod-nnn-rm is 0xc0 or not, ie., it's a register operation
and not memory. So I flag this in fetchdecode{,64}.cc.
This added on the order of 1% performance improvement for
a Win95 boot.
Macroized a few leftover calls to Write_RMV_virtual_xyz()
that didn't get modified in the x86-64 merge. Really, they
just call the real function for now, but I want to have them
available to do direct writes with the guest2host TLB pointers.
440 lines
9.8 KiB
C++
440 lines
9.8 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: logical64.cc,v 1.4 2002-09-20 03:52:58 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::XOR_EqGq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, result_64;
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/* op2_64 is a register, op2_addr is an index of a register */
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 ^ op2_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_XOR64);
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}
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void
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BX_CPU_C::XOR_GqEq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, result_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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result_64 = op1_64 ^ op2_64;
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/* now write result back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), result_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_XOR64);
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}
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void
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BX_CPU_C::XOR_RAXId(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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sum_64 = op1_64 ^ op2_64;
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/* now write sum back to destination */
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RAX = sum_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_XOR64);
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}
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void
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BX_CPU_C::XOR_EqId(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 ^ op2_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_XOR64);
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}
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void
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BX_CPU_C::OR_EqId(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 | op2_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_OR64);
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}
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void
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BX_CPU_C::NOT_Eq(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = ~op1_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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}
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void
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BX_CPU_C::OR_EqGq(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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/* op2_64 is a register, op2_addr is an index of a register */
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 | op2_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_OR64);
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}
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void
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BX_CPU_C::OR_GqEq(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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result_64 = op1_64 | op2_64;
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/* now write result back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), result_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_OR64);
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}
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void
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BX_CPU_C::OR_RAXId(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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sum_64 = op1_64 | op2_64;
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/* now write sum back to destination */
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RAX = sum_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_OR64);
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}
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void
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BX_CPU_C::AND_EqGq(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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/* op2_64 is a register, op2_addr is an index of a register */
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 & op2_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_AND64);
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}
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void
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BX_CPU_C::AND_GqEq(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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result_64 = op1_64 & op2_64;
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/* now write result back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), result_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_AND64);
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}
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void
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BX_CPU_C::AND_RAXId(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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sum_64 = op1_64 & op2_64;
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/* now write sum back to destination */
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RAX = sum_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_AND64);
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}
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void
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BX_CPU_C::AND_EqId(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 & op2_64;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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}
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else {
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Write_RMW_virtual_qword(result_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_AND64);
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}
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void
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BX_CPU_C::TEST_EqGq(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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/* op2_64 is a register, op2_addr is an index of a register */
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 & op2_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_TEST64);
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}
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void
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BX_CPU_C::TEST_RAXId(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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/* op1 is RAX register */
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op1_64 = RAX;
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/* op2 is imm64 */
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op2_64 = (Bit32s) i->Id();
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result_64 = op1_64 & op2_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_TEST64);
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}
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void
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BX_CPU_C::TEST_EqId(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, result_64;
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/* op2 is imm64 */
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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result_64 = op1_64 & op2_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_TEST64);
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}
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